Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Advanced Structures and New Detection Methods for Future High Density Non-volatile Memory Technologies

Alvaro Padilla

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2008-9
January 29, 2008

http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-9.pdf

The proliferation of portable electronic devices has spawned demand for ultra-high-density non-volatile semiconductor memory (NVM). Until recently, aggressive scaling of conventional (flash, SONOS) NVM cell structures (coupled with the use of algorithms that enable the storage of multiple bits of information within every cell) has resulted in a significant increase in NVM storage density. However, additional scaling of these technologies (beyond the 45nm node) is a major challenge due to both short-channel effects (SCE) and the enhanced cell-to-cell variation (in threshold voltage, VT) that results from NVM cell structures with smaller dimensions. This dissertation investigates the use of novel materials, charge detection methods and NVM Field Effect Transistor (FET) structures that (in principle) enhance the scalability of conventional semiconductor flash memory technologies. This assessment proposes solutions (based on materials and structures) that are compatible with conventional CMOS process flows. Chapter 1 introduces the main challenges affecting the scalability of conventional NVM cell structures. Chapter 2 explores the use of high-k dielectrics within the gate-stack of a charge-trapping NVM cell and highlights both the limited benefits obtained with this approach and the need for a new charge detection method that mitigates variation and has reduced sensitivity to charge stored in the complementary bit(s) of the structure. Chapters 3 through 6 explore the use of double-gated Silicon-on-Insulator FET (DG-FET) structures as NVM cells. In Chapter 3, a dual-bit FinFET SONOS NVM cell structure is demonstrated. This structure can utilize either the conventional and/or a novel read method to independently distinguish the digital information stored at either bit. Since the novel read method is less sensitive to charge stored in the complementary bit, its use alone can enhance the scalability of multi-bit NVM cells. In Chapter 4 (5), a novel n-channel (p-channel) dual-bit FinFET-based NVM cell design with two separate gate-sidewall charge-storage sites is presented for the first time. This Gate-Sidewall Storage (GSS) cell design enhances the scalability of conventional SONOS cells since it can utilize a thinner gate-stack EOT and its charge-storage sites are physically separated (which suppresses sensitivity to charge stored in the complementary bit). Finally, Chapter 6 explores the use of (either SONOS or GSS) DG-FET¿s as 4-bit NVM cell structures. In terms of layout efficiency, the optimum practical implementation of these structures involves the use of the Back-Gated FET design, since its use most effectively reduces the size per bit of each unit cell within either NOR- or NAND-type array architectures.

Advisor: Tsu-Jae King Liu


BibTeX citation:

@phdthesis{Padilla:EECS-2008-9,
    Author = {Padilla, Alvaro},
    Title = {Advanced Structures and New Detection Methods for Future High Density Non-volatile Memory Technologies},
    School = {EECS Department, University of California, Berkeley},
    Year = {2008},
    Month = {Jan},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-9.html},
    Number = {UCB/EECS-2008-9},
    Abstract = {The proliferation of portable electronic devices has spawned demand for ultra-high-density non-volatile semiconductor memory (NVM).  Until recently, aggressive scaling of conventional (flash, SONOS) NVM cell structures (coupled with the use of algorithms that enable the storage of multiple bits of information within every cell) has resulted in a significant increase in NVM storage density.  However, additional scaling of these technologies (beyond the 45nm node) is a major challenge due to both short-channel effects (SCE) and the enhanced cell-to-cell variation (in threshold voltage, VT) that results from NVM cell structures with smaller dimensions.
  
This dissertation investigates the use of novel materials, charge detection methods and NVM Field Effect Transistor (FET) structures that (in principle) enhance the scalability of conventional semiconductor flash memory technologies.  This assessment proposes solutions (based on materials and structures) that are compatible with conventional CMOS process flows.  Chapter 1 introduces the main challenges affecting the scalability of conventional NVM cell structures.  Chapter 2 explores the use of high-k dielectrics within the gate-stack of a charge-trapping NVM cell and highlights both the limited benefits obtained with this approach and the need for a new charge detection method that mitigates variation and has reduced sensitivity to charge stored in the complementary bit(s) of the structure.  Chapters 3 through 6 explore the use of double-gated Silicon-on-Insulator FET (DG-FET) structures as NVM cells.  In Chapter 3, a dual-bit FinFET SONOS NVM cell structure is demonstrated.  This structure can utilize either the conventional and/or a novel read method to independently distinguish the digital information stored at either bit.  Since the novel read method is less sensitive to charge stored in the complementary bit, its use alone can enhance the scalability of multi-bit NVM cells.  In Chapter 4 (5), a novel n-channel (p-channel) dual-bit FinFET-based NVM cell design with two separate gate-sidewall charge-storage sites is presented for the first time.  This Gate-Sidewall Storage (GSS) cell design enhances the scalability of conventional SONOS cells since it can utilize a thinner gate-stack EOT and its charge-storage sites are physically separated (which suppresses sensitivity to charge stored in the complementary bit).  Finally, Chapter 6 explores the use of (either SONOS or GSS) DG-FET¿s as 4-bit NVM cell structures. In terms of layout efficiency, the optimum practical implementation of these structures involves the use of the Back-Gated FET design, since its use most effectively reduces the size per bit of each unit cell within either NOR- or NAND-type array architectures.}
}

EndNote citation:

%0 Thesis
%A Padilla, Alvaro
%T Advanced Structures and New Detection Methods for Future High Density Non-volatile Memory Technologies
%I EECS Department, University of California, Berkeley
%D 2008
%8 January 29
%@ UCB/EECS-2008-9
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-9.html
%F Padilla:EECS-2008-9