Vincent Wai-Shan Ng and Seth R. Sanders

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2008-5

January 13, 2008

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-5.pdf

This thesis presents a 12V-to-1.5V Switched-Capacitor dc-dc converter. The overall circuit is a Dickson-type 8-to-1 step down converter in a 0.18um CMOS technology. The power transistors are implemented with native 0.18um 1.8V NMOS and 0.5um 5V NMOS, whereas the power-train capacitors are implemented with off-chip ceramic capacitors. The die is divided into various voltage domains isolated with triple-well nwell structures to ensure that no terminal of any transistor has overstress voltage levels, even though, each terminal itself may be as high as 15V above the substrate voltage level. This circuit shows a peak efficiency of 98% at 50mA load and a maximum load of about 1.5A. Significantly, the efficiency remains at 90% or higher for the load range from 6 mA to 400 mA without need for any mode or switching frequency adjustments. The efficiency at low load condition can be further increased by reducing the switching frequency of the circuit. The active die area is 3 mm2 out of a total area of 9 mm2. All power switches are located at the periphery of the die to minimize on-chip metal resistances, leaving the middle portion of the die empty. The experimental efficiency data matches very well with the theoretical curve. If solder bump pads are used to eliminate bondwires and other interconnect pathways to the printed circuit board, the output referred resistance can be potentially reduced by 50% while reducing the die area by 66%

Advisors: Seth R. Sanders

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BibTeX citation:

@mastersthesis{Ng:EECS-2008-5,
    Author= {Ng, Vincent Wai-Shan and Sanders, Seth R.},
    Title= {A 98% peak efficiency 1.5A 12V-to-1.5V Switched Capacitor dc-dc converter in 0.18um CMOS technology},
    School= {EECS Department, University of California, Berkeley},
    Year= {2008},
    Month= {Jan},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-5.html},
    Number= {UCB/EECS-2008-5},
    Abstract= {This thesis presents a 12V-to-1.5V Switched-Capacitor dc-dc converter. The overall circuit is a Dickson-type 8-to-1 step down converter in a 0.18um CMOS technology. The power transistors are implemented with native 0.18um 1.8V NMOS and 0.5um 5V NMOS, whereas the power-train capacitors are implemented with off-chip ceramic capacitors. The die is divided into various voltage domains isolated with triple-well nwell structures to ensure that no terminal of any transistor has overstress voltage levels, even though, each terminal itself may be as high as 15V above the substrate voltage level. This circuit shows a peak efficiency of 98% at 50mA load and a maximum load of about 1.5A. Significantly, the efficiency remains at 90% or higher for the load range from 6 mA to 400 mA without need for any mode or switching frequency adjustments. The efficiency at low load condition can be further increased by reducing the switching frequency of the circuit. The active die area is 3 mm2 out of a total area of 9 mm2. All power switches are located at the periphery of the die to minimize on-chip metal resistances, leaving the middle portion of the die empty. The experimental efficiency data matches very well with the theoretical curve. If solder bump pads are used to eliminate bondwires and other interconnect pathways to the printed circuit board, the output referred resistance can be potentially reduced by 50% while reducing the die area by 66%},
}

EndNote citation:

%0 Thesis
%A Ng, Vincent Wai-Shan 
%A Sanders, Seth R. 
%T A 98% peak efficiency 1.5A 12V-to-1.5V Switched Capacitor dc-dc converter in 0.18um CMOS technology
%I EECS Department, University of California, Berkeley
%D 2008
%8 January 13
%@ UCB/EECS-2008-5
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-5.html
%F Ng:EECS-2008-5