Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Nanoscale CMOS Modeling

Mohan Vamsi Dunga

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2008-20
March 3, 2008

http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-20.pdf

Since its inception almost four decades ago, the conventional planar bulk silicon MOSFET has been scaled relentlessly in accordance with the Moore's Law. However, as the state-of-the-art MOSFET makes inroads into the nanoscale regime, the traditional scaling solutions are being confronted with fundamental physical limitations stunting the rate of CMOS scaling. The insatiable need for scaled CMOS, primarily driven by the economics of computing market, is forcing researchers world-wide to seek scaling solutions in the form of alternative MOSFET structures and new materials for conventional bulk silicon MOSFET. Scaling also introduces new electrical behavior into MOSFETs which had hitherto been unknown or at the least imperceptible. Compact models describing the physics and operation of state-of-the-art bulk planar bulk MOSFETs and new CMOS scaling alternatives are imperative not only for short-term technology design and circuit-level explorations but also for long term product development. The goal of this dissertation is to develop accurate and efficient compact models for emerging nanoscale CMOS devices through a sound understanding of the underlying physics. New MOSFET architectures - Multi-Gate FETs (MG-FETs) which employ the use of multiple gate electrodes to thwart the deleterious short channel efforts in scaled transistors hold promise to scale CMOS beyond 22nm technology node. The multiple gates in a MG-FET can be electrically interconnected as in FinFETs or can be biased independently as in independent MG-FETs. Surface-potential based compact models describing the electrical characteristics - terminal currents, charges and capacitances - are developed for both categories of MG-FETs. Full scale compact models are developed to describe the start-of-the-art MG-FET technologies. While new MOSFET architectures are being evaluated, the traditional cost-effective single-gate bulk planar CMOS is still breaking scaling and performance barriers through the use of process-induced strain. A new non-process-specific layout-dependent mobility model for mobility enhancement through process induced strain is developed to improve the modeling of state-of-the-art bulk MOSFETs. Furthermore, the scaled MOSFETs are experiencing increased variability in low-frequency noise characteristics. A thorough understanding of the underlying physics is presented together with a new statistical model for modeling the low frequency noise in scaled MOSFETs.

Advisor: Ali Niknejad


BibTeX citation:

@phdthesis{Dunga:EECS-2008-20,
    Author = {Dunga, Mohan Vamsi},
    Title = {Nanoscale CMOS Modeling},
    School = {EECS Department, University of California, Berkeley},
    Year = {2008},
    Month = {Mar},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-20.html},
    Number = {UCB/EECS-2008-20},
    Abstract = {Since its inception almost four decades ago, the conventional planar bulk silicon MOSFET has been scaled relentlessly in accordance with the Moore's Law.  However, as the state-of-the-art MOSFET makes inroads into the nanoscale regime, the traditional scaling solutions are being confronted with fundamental physical limitations stunting the rate of CMOS scaling. The insatiable need for scaled CMOS, primarily driven by the economics of computing market, is forcing researchers world-wide to seek scaling solutions in the form of alternative MOSFET structures and new materials for conventional bulk silicon MOSFET. Scaling also introduces new electrical behavior into MOSFETs which had hitherto been unknown or at the least imperceptible. Compact models describing the physics and operation of state-of-the-art bulk planar bulk MOSFETs and new CMOS scaling alternatives are imperative not only for short-term technology design and circuit-level explorations but also for long term product development. The goal of this dissertation is to develop accurate and efficient compact models for emerging nanoscale CMOS devices through a sound understanding of the underlying physics.

New MOSFET architectures - Multi-Gate FETs (MG-FETs) which employ the use of multiple gate electrodes to thwart the deleterious short channel efforts in scaled transistors hold promise to scale CMOS beyond 22nm technology node. The multiple gates in a MG-FET can be electrically interconnected as in FinFETs or can be biased independently as in independent MG-FETs. Surface-potential based compact models describing the electrical characteristics - terminal
currents, charges and capacitances - are developed for both
categories of MG-FETs. Full scale compact models are developed to describe the start-of-the-art MG-FET technologies.

While new MOSFET architectures are being evaluated, the traditional cost-effective single-gate bulk planar CMOS is still breaking scaling and performance barriers through the use of process-induced strain. A new non-process-specific layout-dependent mobility model for mobility enhancement through process induced strain is developed to improve the modeling of state-of-the-art bulk MOSFETs. Furthermore, the scaled MOSFETs are experiencing increased variability in low-frequency noise characteristics. A thorough understanding of the underlying physics is presented together with a new statistical model for modeling the low frequency noise in scaled MOSFETs.}
}

EndNote citation:

%0 Thesis
%A Dunga, Mohan Vamsi
%T Nanoscale CMOS Modeling
%I EECS Department, University of California, Berkeley
%D 2008
%8 March 3
%@ UCB/EECS-2008-20
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-20.html
%F Dunga:EECS-2008-20