Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Synchronous Reactive Communication: Generalization, Implementation, and Optimization

Guoqiang Wang

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2008-178
December 19, 2008

http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-178.pdf

A fundamental asset of a model-based development process is the capability of providing an automatic implementation of the model that preserves its semantics, and at the same time makes efficient use of the execution platform resources. Synchronous Reactive (SR) models are increasingly used in model-based design flows for the development of embedded control applications. The implementation of communication links between functional blocks in an SR model requires buffering schemes and access procedures implemented at the kernel level. Platform-based design methodology is introduced to synthesize a real-time operating system when implementing SR models. Previous research has proposed two methods for sizing the communication buffer. This dissertation demonstrates how it is possible to improve on the state of the art, providing not only tighter bounds by leveraging task timing information, but also an approach that is capable of dealing with a more general model and implementation platform configuration. To achieve rigorous model semantics, this dissertation presents semantics preserving implementations of SR communication for multi-rate systems on single processor architectures. The implemented protocols define the assignment of indices of shared buffers to writer and reader tasks at activation time, rather than at execution time. Two constant-time portable solutions are developed in the C language and with the automotive OSEK OS standard. Run-time complexity and memory requirements are discussed for the two protocol implementations, and tradeoffs are analyzed. This dissertation completes the SR model-based design flow by supporting automatic code generation for the double buffer and the dynamic buffering protocols. To support software portability and reusability, the ePICos18, compliant to the OSEK OS standard, is used. The generated code is validated by emulation on the PIC18F452 microcontroller through the MPLAB IDE simulator. An implementation of communication links with a minimum buffer size is often desirable, but it may require a longer access time and it may also lead to the violation of deadline constraints in real-time applications. This dissertation demonstrates the feasibility of an MILP-based optimization approach that provides the minimum memory implementation of a set of communication channels within the deadline constraints of the tasks.

Advisor: Alberto L. Sangiovanni-Vincentelli


BibTeX citation:

@phdthesis{Wang:EECS-2008-178,
    Author = {Wang, Guoqiang},
    Title = {Synchronous Reactive Communication: Generalization, Implementation, and Optimization},
    School = {EECS Department, University of California, Berkeley},
    Year = {2008},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-178.html},
    Number = {UCB/EECS-2008-178},
    Abstract = {A fundamental asset of a model-based development process is the capability of providing an automatic implementation of the model that preserves its semantics, and at the same time makes efficient use of the execution platform resources. Synchronous Reactive (SR) models are increasingly used in model-based design flows for the
development of embedded control applications.

The implementation of communication links between functional blocks in an SR model requires buffering schemes and access procedures implemented at the kernel level.
Platform-based design methodology is introduced to synthesize a real-time operating system when implementing SR models. Previous research has proposed two methods for sizing the communication buffer. This dissertation demonstrates how it is possible to improve on the state of the art, providing not only tighter bounds by leveraging task timing information, but also an approach that is capable of dealing with a more general model and implementation platform configuration.

To achieve rigorous model semantics, this dissertation presents semantics preserving implementations of SR communication for multi-rate systems on single processor architectures. The implemented protocols define the assignment of indices of shared buffers to writer and reader tasks at activation time, rather than at execution time. Two constant-time portable solutions are developed in the C language and with the automotive OSEK OS standard. Run-time complexity and memory requirements are discussed
for the two protocol implementations, and tradeoffs are analyzed. This dissertation completes the SR model-based design flow by supporting automatic code generation for the double buffer and the dynamic buffering protocols. To support software portability and reusability, the ePICos18, compliant to the OSEK OS standard, is used. The generated code is validated by emulation on the PIC18F452 microcontroller through the MPLAB IDE simulator.

An implementation of communication links with a minimum buffer size is often desirable, but it may require a longer access time and it may also lead to the violation of deadline constraints in real-time applications. This dissertation demonstrates the feasibility of an MILP-based optimization approach that provides the minimum memory
implementation of a set of communication channels within the
deadline constraints of the tasks.}
}

EndNote citation:

%0 Thesis
%A Wang, Guoqiang
%T Synchronous Reactive Communication: Generalization, Implementation, and Optimization
%I EECS Department, University of California, Berkeley
%D 2008
%8 December 19
%@ UCB/EECS-2008-178
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-178.html
%F Wang:EECS-2008-178