0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VI.
Laszlo Petho and Anita Pongracz
EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2008-168
December 18, 2008
http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-168.pdf
This report presents details of the fourth six-inch baseline run, CMOS180, where a moderately complex 0.35 μm twin-well, silicided, LOCOS, Mix&Match photo process was implemented. This process was based on the first 0.35 μm six-inch run, CMOS161. Different research circuits (IC/MEMS) were placed in the drop-in area: ring oscillators, a MEMS design, a hyperacuity chip and several different memory circuits.
BibTeX citation:
@techreport{Petho:EECS-2008-168,
Author = {Petho, Laszlo and Pongracz, Anita},
Title = {0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VI.},
Institution = {EECS Department, University of California, Berkeley},
Year = {2008},
Month = {Dec},
URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-168.html},
Number = {UCB/EECS-2008-168},
Abstract = {This report presents details of the fourth six-inch baseline run, CMOS180, where a moderately complex 0.35 μm twin-well, silicided, LOCOS, Mix&Match photo process was implemented. This process was based on the first 0.35 μm six-inch run, CMOS161. Different research circuits (IC/MEMS) were placed in the drop-in area: ring oscillators, a MEMS design, a hyperacuity chip and several different memory circuits.}
}
EndNote citation:
%0 Report %A Petho, Laszlo %A Pongracz, Anita %T 0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VI. %I EECS Department, University of California, Berkeley %D 2008 %8 December 18 %@ UCB/EECS-2008-168 %U http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-168.html %F Petho:EECS-2008-168