Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report V.

A. Pongracz and G. Vida

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2007-26
February 9, 2007

http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-26.pdf

This report presents details of the third six-inch baseline run, CMOS170, where a moderately complex 0.35 µm twin-well, silicided process was used. This process was based on the first six-inch 0.35 µm run, CMOS161. Different research circuits (IC/MEMS) were placed in the drop-in area, i.e. ring oscillators, a MEMS design, a hyperacuity chip and several different memory circuits. A more complex (triple metal) process flow consisting of 66 steps was introduced by this version of the 0.35 µm process, with the main objective of matching N-channel and P-channel threshold voltages (Vt, absolute values). According to simulations the NMOS threshold voltage was matched to the PMOS values by decreasing the NMOS Vt implantation dose.


BibTeX citation:

@techreport{Pongracz:EECS-2007-26,
    Author = {Pongracz, A. and Vida, G.},
    Title = {0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report V.},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2007},
    Month = {Feb},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-26.html},
    Number = {UCB/EECS-2007-26},
    Abstract = {This report presents details of the third six-inch baseline run, CMOS170, where a moderately complex 0.35 µm twin-well, silicided process was used. This process was based on the first six-inch 0.35 µm run, CMOS161. Different research circuits (IC/MEMS) were placed in the drop-in area, i.e. ring oscillators, a MEMS design, a hyperacuity chip and several different memory circuits. A more complex (triple metal) process flow consisting of 66 steps was introduced by this version of the 0.35 µm process, with the main objective of matching N-channel and P-channel threshold voltages (Vt, absolute values). According to simulations the NMOS threshold voltage was matched to the PMOS values by decreasing the NMOS Vt implantation dose.}
}

EndNote citation:

%0 Report
%A Pongracz, A.
%A Vida, G.
%T 0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report V.
%I EECS Department, University of California, Berkeley
%D 2007
%8 February 9
%@ UCB/EECS-2007-26
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-26.html
%F Pongracz:EECS-2007-26