Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

CMOS Power Amplifiers for Wireless Communications

King Chun Tsai

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2007-161
December 18, 2007

http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-161.pdf

The advancement of CMOS technology has enabled an unprecedented level of integration in modern low cost, small form-factor and low power wireless devices. While Power Amplifies (PAs) are key components in wireless transceivers, their realization and integration in standard CMOS technology is hindered by a number of technological challenges. One fundamental challenge of high efficiency CMOS PA realization is the low breakdown voltage of thin gate oxide devices. It forces high output power CMOS PAs to operate under high-current, low-impedance levels where they are vulnerable to parasitic losses. Other challenges include the limited intrinsic gain and large parasitic capacitance and resistance of CMOS transistors, as well as the lack of high quality factor monolithic passive components. This thesis addresses these challenges and demonstrates an RF CMOS power amplifier that is suitable for amplification of constant envelope modulated signals that are widely used in cellular systems such as GSM. The key design innovations include (1) the use of a differential switch-mode Class-E structure to optimize power efficiency, extend power capacity, and minimize the impact of substrate noise injection; (2) the use of injection locking technique to significantly reduce the input driving requirement of large transistors; and (3) the design of a compact hybrid balun to interface the differential PA with any conventional signal-ended RF load. The effectiveness of these techniques is demonstrated in a PA prototype that is fabricated in a standard 0.35um CMOS process. The prototype operates up to 2GHz and is capable of delivering 1 Watt of output power with a 48% power-added efficiency (41% including the balun). Comparing with its predecessors, this prototype demonstrates a new level of operational frequency, output power and power efficiency achievable by CMOS power amplifiers.

Advisor: Paul R. Gray


BibTeX citation:

@phdthesis{Tsai:EECS-2007-161,
    Author = {Tsai, King Chun},
    Title = {CMOS Power Amplifiers for Wireless Communications},
    School = {EECS Department, University of California, Berkeley},
    Year = {2007},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-161.html},
    Number = {UCB/EECS-2007-161},
    Abstract = {The advancement of CMOS technology has enabled an unprecedented level of integration in modern low cost, small form-factor and low power wireless devices. While Power Amplifies (PAs) are key components in wireless transceivers, their realization and integration in standard CMOS technology is hindered by a number of technological challenges.

One fundamental challenge of high efficiency CMOS PA realization is the low breakdown voltage of thin gate oxide devices. It forces high output power CMOS PAs to operate under high-current, low-impedance levels where they are vulnerable to parasitic losses. Other challenges include the limited intrinsic gain and large parasitic capacitance and resistance of CMOS transistors, as well as the lack of high quality factor monolithic passive components.

This thesis addresses these challenges and demonstrates an RF CMOS power amplifier that is suitable for amplification of constant envelope modulated signals that are widely used in cellular systems such as GSM. The key design innovations include (1) the use of a differential switch-mode Class-E structure to optimize power efficiency, extend power capacity, and minimize the impact of substrate noise injection; (2) the use of injection locking technique to significantly reduce the input driving requirement of large transistors; and (3) the design of a compact hybrid balun to interface the differential PA with any conventional signal-ended RF load. The effectiveness of these techniques is demonstrated in a PA prototype that is fabricated in a standard 0.35um CMOS process. The prototype operates up to 2GHz and is capable of delivering 1 Watt of output power with a 48% power-added efficiency (41% including the balun). Comparing with its predecessors, this prototype demonstrates a new level of operational frequency, output power and power efficiency achievable by CMOS power amplifiers.}
}

EndNote citation:

%0 Thesis
%A Tsai, King Chun
%T CMOS Power Amplifiers for Wireless Communications
%I EECS Department, University of California, Berkeley
%D 2007
%8 December 18
%@ UCB/EECS-2007-161
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-161.html
%F Tsai:EECS-2007-161