Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Spatial Modeling of Gate Length Variation for Process-Design Co-Optimization

Paul David Friedberg

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2007-157
December 17, 2007

http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-157.pdf

Variability in circuit performance is a rapidly growing concern in the semiconductor industry, and a potential roadblock in circuit design. In order to combat the negative impact of manufacturing variations on circuit performance, two approaches can be taken. The first approach emphasizes process control from a manufacturing perspective, in an effort to directly reduce the variation in device parameters; the second approach attacks the problem from the design perspective, where specific design methodologies can be developed to decrease a circuit¿s sensitivity to process variation. Both approaches rely on exploration through the use of simulation frameworks that capture the detailed interaction between manufacturing variation and the resulting circuit performance variability. With such a framework, one can determine the most deleterious sources of device parameter variation, and then identify the effects of a certain flavor of process control, or search for sensitivity-reducing design techniques. In order for the simulation framework to be truly useful, however, an accurate model of the relationship between variation and variability is required. This work explains how a rigorous spatial statistical description of the manufacturing variation is a crucial aspect for the simulation framework. Using an array of test structures, spatial variation in critical dimension is exhaustively characterized. Then, a variety of statistical descriptions of spatial CD variation are instantiated in an analytical, macromodel-based Monte Carlo simulation framework. Based on evaluation of these statistical descriptions against one another, it is shown that a full decomposition of deterministic variation is required for optimal accuracy. Moreover, it is shown that such a decomposition of variance accounts for virtually all spatial autocorrelation in CD. Finally, it is shown that employing a simplified statistical description (as is commonly done in existing MC frameworks) that relies on spatial autocorrelation to capture deterministic variation overestimates the impact of variation on performance variability.

Advisor: Costas J. Spanos


BibTeX citation:

@phdthesis{Friedberg:EECS-2007-157,
    Author = {Friedberg, Paul David},
    Title = {Spatial Modeling of Gate Length Variation for Process-Design Co-Optimization},
    School = {EECS Department, University of California, Berkeley},
    Year = {2007},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-157.html},
    Number = {UCB/EECS-2007-157},
    Abstract = {Variability in circuit performance is a rapidly growing concern in the semiconductor industry, and a potential roadblock in circuit design.  In order to combat the negative impact of manufacturing variations on circuit performance, two approaches can be taken. The first approach emphasizes process control from a manufacturing perspective, in an effort to directly reduce the variation in device parameters; the second approach attacks the problem from the design perspective, where specific design methodologies can be developed to decrease a circuit¿s sensitivity to process variation.  Both approaches rely on exploration through the use of simulation frameworks that capture the detailed interaction between manufacturing variation and the resulting circuit performance variability.  With such a framework, one can determine the most deleterious sources of device parameter variation, and then identify the effects of a certain flavor of process control, or search for sensitivity-reducing design techniques.
  
In order for the simulation framework to be truly useful, however, an accurate model of the relationship between variation and variability is required.  This work explains how a rigorous spatial statistical description of the manufacturing variation is a crucial aspect for the simulation framework.  Using an array of test structures, spatial variation in critical dimension is exhaustively characterized.  Then, a variety of statistical descriptions of spatial CD variation are instantiated in an analytical, macromodel-based Monte Carlo simulation framework.  Based on evaluation of these statistical descriptions against one another, it is shown that a full decomposition of deterministic variation is required for optimal accuracy.  Moreover, it is shown that such a decomposition of variance accounts for virtually all spatial autocorrelation in CD.  Finally, it is shown that employing a simplified statistical description (as is commonly done in existing MC frameworks) that relies on spatial autocorrelation to capture deterministic variation overestimates the impact of variation on performance variability.}
}

EndNote citation:

%0 Thesis
%A Friedberg, Paul David
%T Spatial Modeling of Gate Length Variation for Process-Design Co-Optimization
%I EECS Department, University of California, Berkeley
%D 2007
%8 December 17
%@ UCB/EECS-2007-157
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-157.html
%F Friedberg:EECS-2007-157