Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Ultra Low Power Clock Generation

Asako Toda and Jan M. Rabaey

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2007-101
August 16, 2007

http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-101.pdf

In this research, MOS Current Mode Logic (MCML) in sub-threshold (sub-Vth) operation has been fist time investigated and applied to clock generation circuitry. Sub-threshold operation is known to be the optimum point of operation in terms of power-speed metric, however, it is sensitive to temperature and voltage variation due to the exponential nature of this region. In order to achieve robust logic operation over PVT variation, voltage swing from high to low logic level is controlled both statically and dynamically : The static control has been done by setting enough voltage swing to convey logic level to the next stage. A DC input-output model is proposed to analyze process variation and mismatch effect, and together with Monte Carlo simulation result, the necessary voltage swing was specified. The voltage swing is also controlled dynamically by replica bias circuit and a proposed current bias circuit . A study on coupling phenomena of ring oscillators stemmed from phase noise analysis, and mathematical behavior model was validated by Spectre simulation. In the end of research, sub-threshold MCML is applied to 3-stage ring oscillators to generate 2G-Hz clock signal with 40uA and 1.25V power consumption.One hundred ring oscillators were implemented on a same die of 90nm CMOS process to collect the data of not only variation effect but also coupling effect of oscillators.

Advisor: Jan M. Rabaey


BibTeX citation:

@mastersthesis{Toda:EECS-2007-101,
    Author = {Toda, Asako and Rabaey, Jan M.},
    Title = {Ultra Low Power Clock Generation},
    School = {EECS Department, University of California, Berkeley},
    Year = {2007},
    Month = {Aug},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-101.html},
    Number = {UCB/EECS-2007-101},
    Abstract = { In this research, MOS Current Mode Logic (MCML) in sub-threshold (sub-Vth) operation has been fist time investigated and applied to clock generation circuitry. 
 Sub-threshold operation is known to be the optimum point of operation in terms of power-speed metric, however, it is sensitive to temperature and voltage variation due to the exponential nature of this region. In order to achieve robust logic operation over PVT variation, voltage swing from high to low logic level is controlled both statically and dynamically :
The static control has been done by setting enough voltage swing to convey logic level to the next stage. A DC input-output model is proposed to analyze process variation and mismatch effect, and together with Monte Carlo simulation result, the  necessary voltage swing was specified. 
The voltage swing is also controlled dynamically by replica bias circuit and a proposed current bias circuit .
 A study on coupling phenomena of ring oscillators stemmed from phase noise analysis, and mathematical behavior model was validated by Spectre simulation.
 In the end of research, sub-threshold MCML is applied to 3-stage ring oscillators to generate 2G-Hz clock signal with 40uA and 1.25V power consumption.One hundred ring oscillators were implemented on a same die of 90nm CMOS process to collect the data of not only variation effect but also coupling effect of oscillators.}
}

EndNote citation:

%0 Thesis
%A Toda, Asako
%A Rabaey, Jan M.
%T Ultra Low Power Clock Generation
%I EECS Department, University of California, Berkeley
%D 2007
%8 August 16
%@ UCB/EECS-2007-101
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2007/EECS-2007-101.html
%F Toda:EECS-2007-101