Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Low Power Design Automation

David Graeme Chinnery

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2006-182
December 18, 2006

http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-182.pdf

We investigate the differences in power between application-specific integrated circuits (ASICs), designed in an automated design methodology, and custom integrated circuits with examples from 0.6um to 0.13um CMOS. The ASICs dissipate 3 to 7x more power than custom integrated circuits. We quantify factors contributing to the power gap with analytical models and empirical data. We discuss the shortcomings of typical synthesis flows, and the changes to tools and standard cell libraries that are necessary to reduce power. The most significant opportunity for power reduction in ASICs is using microarchitectural techniques to maintain performance while reducing power via voltage scaling. By using high performance and low power techniques that can be integrated within an EDA methodology, we believe that the power gap between ASIC and custom designs may be closed to within 2.6x. One such approach is to use high Vdd and low Vth on critical paths, and low Vdd and high Vth elsewhere to reduce the power. We formulate optimization of Vdd, Vth, and gate sizes as a convex geometric program with posynomial models of gate delay and power. Dual Vdd and dual Vth provide up to 18% power saving versus optimal voltage scaling with single Vdd and single Vth. The geometric programming runtime grows cubically with circuit size, making it computationally infeasible for circuits of an interesting size to designers. Existing circuit sizing heuristics that proceed in the manner of TILOS are fast, having quadratic runtime growth, but can be suboptimal. We develop a gate sizing approach using linear programming (LP) which achieves on average 16.3% power savings versus Design Compiler, a commercial synthesis tool. Our approach has up to quadratic runtime growth, making it scalable to larger circuit sizes. The dual-Vdd/dual-Vth/sizing results with the LP approach average 5% to 13% lower power than the best alternate approaches that we know of for this problem. We find that dual Vth reduces power by 16% on average and up to 26% versus using a single Vth; whereas dual Vdd only reduces power by 4% on average and up to 14% versus using a single Vdd.

Advisor: Kurt Keutzer


BibTeX citation:

@phdthesis{Chinnery:EECS-2006-182,
    Author = {Chinnery, David Graeme},
    Title = {Low Power Design Automation},
    School = {EECS Department, University of California, Berkeley},
    Year = {2006},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-182.html},
    Number = {UCB/EECS-2006-182},
    Abstract = {We investigate the differences in power between application-specific integrated circuits (ASICs), designed in an automated design methodology, and custom integrated circuits with examples from 0.6um to 0.13um CMOS. The ASICs dissipate 3 to 7x more power than custom integrated circuits. We quantify factors contributing to the power gap with analytical models and empirical data. We discuss the shortcomings of typical synthesis flows, and the changes to tools and standard cell libraries that are necessary to reduce power.
The most significant opportunity for power reduction in ASICs is using microarchitectural techniques to maintain performance while reducing power via voltage scaling. By using high performance and low power techniques that can be integrated within an EDA methodology, we believe that the power gap between ASIC and custom designs may be closed to within 2.6x. One such approach is to use high Vdd and low Vth on critical paths, and low Vdd and high Vth elsewhere to reduce the power.
We formulate optimization of Vdd, Vth, and gate sizes as a convex geometric program with posynomial models of gate delay and power. Dual Vdd and dual Vth provide up to 18% power saving versus optimal voltage scaling with single Vdd and single Vth. The geometric programming runtime grows cubically with circuit size, making it computationally infeasible for circuits of an interesting size to designers. 
Existing circuit sizing heuristics that proceed in the manner of TILOS are fast, having quadratic runtime growth, but can be suboptimal. We develop a gate sizing approach using linear programming (LP) which achieves on average 16.3% power savings versus Design Compiler, a commercial synthesis tool. Our approach has up to quadratic runtime growth, making it scalable to larger circuit sizes. 
The dual-Vdd/dual-Vth/sizing results with the LP approach average 5% to 13% lower power than the best alternate approaches that we know of for this problem. We find that dual Vth reduces power by 16% on average and up to 26% versus using a single Vth; whereas dual Vdd only reduces power by 4% on average and up to 14% versus using a single Vdd.}
}

EndNote citation:

%0 Thesis
%A Chinnery, David Graeme
%T Low Power Design Automation
%I EECS Department, University of California, Berkeley
%D 2006
%8 December 18
%@ UCB/EECS-2006-182
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-182.html
%F Chinnery:EECS-2006-182