Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Fully Integrated CMOS Power Amplifier

Gang Liu

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2006-162
December 6, 2006

http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-162.pdf

Today¿s consumers demand wireless systems that are low-cost, power efficient, reliable and have a small form-factor. High levels of integration are desired to reduce cost and achieve compact form factor for high volume applications. Hence the long term vision or goal for wireless transceivers is to merge as many components as possible, if not all, to a single die in an inexpensive technology. Therefore, there is a growing interest in utilizing CMOS technologies for RF power amplifiers (PAs). Although several advances have been made recently to enable full integration of PAs in CMOS, it is still among the most difficult challenges in achieving a truly single-chip radio system in CMOS. This is exacerbated by supply voltage reduction due to CMOS technology scaling and on-chip passive losses due to the conductive substrate used in deep submicron CMOS processes. Efficiency is one of the most important metrics in the design of power amplifiers. Conventional designs give maximum efficiency only at a single power level, usually near the maximum rated power for the amplifier. As the output power is backed off from that single point, the efficiency drops rapidly. However, power back-off is inevitable in today¿s wireless communication systems. To date, there has been relatively little research on the design of a CMOS PA targeting good average efficiency. A new transformer combining architecture, which is suitable in designing highly efficient PAs in CMOS processes, is proposed to address this issue. A prototype was implemented with only thin-oxide transistors in a 0.13-μm RF-CMOS process to demonstrate the concept. Experimental results validate our concept and demonstrate the feasibility of highly efficiency, fully integrated power amplifiers in CMOS technologies.

Advisor: Tsu-Jae King Liu and Ali Niknejad


BibTeX citation:

@phdthesis{Liu:EECS-2006-162,
    Author = {Liu, Gang},
    Title = {Fully Integrated CMOS Power Amplifier},
    School = {EECS Department, University of California, Berkeley},
    Year = {2006},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-162.html},
    Number = {UCB/EECS-2006-162},
    Abstract = {Today¿s consumers demand wireless systems that are low-cost, power efficient, reliable and have a small form-factor.  High levels of integration are desired to reduce cost and achieve compact form factor for high volume applications.  Hence the long term vision or goal for wireless transceivers is to merge as many components as possible, if not all, to a single die in an inexpensive technology.  Therefore, there is a growing interest in utilizing CMOS technologies for RF power amplifiers (PAs).  Although several advances have been made recently to enable full integration of PAs in CMOS, it is still among the most difficult challenges in achieving a truly single-chip radio system in CMOS.  This is exacerbated by supply voltage reduction due to CMOS technology scaling and on-chip passive losses due to the conductive substrate used in deep submicron CMOS processes.
	Efficiency is one of the most important metrics in the design of power amplifiers.  Conventional designs give maximum efficiency only at a single power level, usually near the maximum rated power for the amplifier.  As the output power is backed off from that single point, the efficiency drops rapidly.  However, power back-off is inevitable in today¿s wireless communication systems. 
	To date, there has been relatively little research on the design of a CMOS PA targeting good average efficiency.  A new transformer combining architecture, which is suitable in designing highly efficient PAs in CMOS processes, is proposed to address this issue.  A prototype was implemented with only thin-oxide transistors in a 0.13-μm RF-CMOS process to demonstrate the concept.  Experimental results validate our concept and demonstrate the feasibility of highly efficiency, fully integrated power amplifiers in CMOS technologies.}
}

EndNote citation:

%0 Thesis
%A Liu, Gang
%T Fully Integrated CMOS Power Amplifier
%I EECS Department, University of California, Berkeley
%D 2006
%8 December 6
%@ UCB/EECS-2006-162
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-162.html
%F Liu:EECS-2006-162