Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

The Case for the Precision Timed (PRET) Machine

Stephen Edwards and Edward A. Lee

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2006-149
November 17, 2006

http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-149.pdf

We argue that at least for embedded software applications, computer architecture, software, and networking have gone too far down the path of emphasizing average case performance over timing predictability. In architecture, techniques such as multi-level caches and deep pipelines with dynamic dispatch and speculative execution make worst-case execution times (WCET) highly dependent on both implementation details of the processor and on the context in which the software is executed. Yet virtually all real-time programming methodologies depend on WCET. When timing properties are important in the software and when concurrent execution is affected by timing, the result is brittle designs. In this paper, we argue for precision timed (PRET) machines, which deliver high performance, but not at the expense of timing predictability. We summarize a number of research approaches that can be used to create PRET machines, and discuss how the software, operating system, and networking abstractions built above the machine architecture will have to change.


BibTeX citation:

@techreport{Edwards:EECS-2006-149,
    Author = {Edwards, Stephen and Lee, Edward A.},
    Title = {The Case for the Precision Timed (PRET) Machine},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2006},
    Month = {Nov},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-149.html},
    Number = {UCB/EECS-2006-149},
    Abstract = {We argue that at least for embedded software applications, computer architecture, software, and networking have gone too far down the path of emphasizing average case performance over timing predictability. In architecture, techniques such as multi-level caches and deep pipelines with dynamic dispatch and speculative execution make worst-case execution times (WCET) highly dependent on both implementation details of the processor and on the context in which the software is executed. Yet virtually all real-time programming methodologies depend on WCET. When timing properties are important in the software and when concurrent execution is affected by timing, the result is brittle designs. In this paper, we argue for precision timed (PRET) machines, which deliver high performance, but not at the expense of timing predictability. We summarize a number of research approaches that can be used to create PRET machines, and discuss how the software, operating system, and networking abstractions built above the machine architecture will have to change.}
}

EndNote citation:

%0 Report
%A Edwards, Stephen
%A Lee, Edward A.
%T The Case for the Precision Timed (PRET) Machine
%I EECS Department, University of California, Berkeley
%D 2006
%8 November 17
%@ UCB/EECS-2006-149
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-149.html
%F Edwards:EECS-2006-149