Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform

Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, David Patterson, Jan Rabaey and John Wawrzynek

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-05-1412
September 2005

http://www.eecs.berkeley.edu/Pubs/TechRpts/2005/CSD-05-1412.pdf

Desktop processor architectures have crossed a critical threshold. Manufactures have given up attempting to extract ever more performance from a single core and instead have turned to multi-core designs. While straightforward approaches to the architecture of multi-core processors are sufficient for small designs (2-4 cores), little is really known how to build, program, or manage systems of 64 to 1024 processors. Unfortunately, the computer architecture community lacks the basic infrastructure tools required to carry out this research. While simulation has been adequate for single-processor research, significant use of simplified modeling and statistical sampling is required to work in the 2-16 processing core space. Invention is required for architecture research at the level of 64-1024 cores.

Fortunately, Moore's law has not only enabled these dense multi-core chips, it has also enabled extremely dense FPGAs. Today, for a few hundred dollars, undergraduates can work with an FPGA prototype board with almost as many gates as a Pentium. Given the right support, the research community can capitalize on this opportunity too. Today, one to two dozen cores can be programmed into a single FPGA. With multiple FPGAs on a board and multiple boards in a system, large complex architectures can be explored. To make this happen, however, requires a significant amount of infrastructure in hardware, software, and what we call "gateware", the register-transfer level models that fill the FGPAs. While it is possible for each research group to create these boards, design the gateware, and create this infrastructure in isolation, significant benefits can be had by pooling our collective resources.

Such a system would not just invigorate multiprocessors research in the architecture community. Since processors cores can run at 100 to 200 MHz, a large scale multiprocessor would be fast enough to run operating systems and large programs at speeds sufficient to support software research. Moreover, there is a new generation of FPGAs every 18 months that is roughly twice as fast and with capacity for twice as many cores, so future multiboard FPGA systems are even more attractive. Hence, we believe such a system would accelerate research across all the fields that touch multiple processors: operating systems, compilers, debuggers, programming languages, scientific libraries, and so on. Thus the acronymn RAMP, for Research Accelerator for Multiple Processors.

This project intends to foster just such a community endeavor. By leveraging the work that each of us was going to do anyway in isolation, we can create a shared infrastructure for architecture research. Furthermore, by pooling our resources in hardware design we can reduce the risk each of us undertakes by designing hardware prototypes ourselves. Finally, by creating shared and supported baseline platforms for multi-core architectures we can jump start the required architecture and critical software research that the field needs.


BibTeX citation:

@techreport{Arvind:CSD-05-1412,
    Author = {Arvind,  and Asanovic, Krste and Chiou, Derek and Hoe, James C. and Kozyrakis, Christoforos and Lu, Shih-Lien and Oskin, Mark and Patterson, David and Rabaey, Jan and Wawrzynek, John},
    Title = {RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2005},
    Month = {Sep},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2005/6513.html},
    Number = {UCB/CSD-05-1412},
    Abstract = {Desktop processor architectures have crossed a critical threshold. Manufactures have given up attempting to extract ever more performance from a single core and instead have turned to multi-core designs. While straightforward approaches to the architecture of multi-core processors are sufficient for small designs (2-4 cores), little is really known how to build, program, or manage systems of 64 to 1024 processors. Unfortunately, the computer architecture community lacks the basic infrastructure tools required to carry out this research. While simulation has been adequate for single-processor research, significant use of simplified modeling and statistical sampling is required to work in the 2-16 processing core space. Invention is required for architecture research at the level of 64-1024 cores. <p> Fortunately, Moore's law has not only enabled these dense multi-core chips, it has also enabled extremely dense FPGAs. Today, for a few hundred dollars, undergraduates can work with an FPGA prototype board with almost as many gates as a Pentium. Given the right support, the research community can capitalize on this opportunity too. Today, one to two dozen cores can be programmed into a single FPGA. With multiple FPGAs on a board and multiple boards in a system, large complex architectures can be explored. To make this happen, however, requires a significant amount of infrastructure in hardware, software, and what we call "gateware", the register-transfer level models that fill the FGPAs. While it is possible for each research group to create these boards, design the gateware, and create this infrastructure in isolation, significant benefits can be had by pooling our collective resources. <p> Such a system would not just invigorate multiprocessors research in the architecture community. Since processors cores can run at 100 to 200 MHz, a large scale multiprocessor would be fast enough to run operating systems and large programs at speeds sufficient to support software research. Moreover, there is a new generation of FPGAs every 18 months that is roughly twice as fast and with capacity for twice as many cores, so future multiboard FPGA systems are even more attractive. Hence, we believe such a system would accelerate research across all the fields that touch multiple processors: operating systems, compilers, debuggers, programming languages, scientific libraries, and so on. Thus the acronymn RAMP, for Research Accelerator for Multiple Processors. <p>This project intends to foster just such a community endeavor. By leveraging the work that each of us was going to do anyway in isolation, we can create a shared infrastructure for architecture research. Furthermore, by pooling our resources in hardware design we can reduce the risk each of us undertakes by designing hardware prototypes ourselves. Finally, by creating shared and supported baseline platforms for multi-core architectures we can jump start the required architecture and critical software research that the field needs.}
}

EndNote citation:

%0 Report
%A Arvind, 
%A Asanovic, Krste
%A Chiou, Derek
%A Hoe, James C.
%A Kozyrakis, Christoforos
%A Lu, Shih-Lien
%A Oskin, Mark
%A Patterson, David
%A Rabaey, Jan
%A Wawrzynek, John
%T RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform
%I EECS Department, University of California, Berkeley
%D 2005
%@ UCB/CSD-05-1412
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2005/6513.html
%F Arvind:CSD-05-1412