Design Optimization of Ultra-Scaled Transistors and the Impact of Process Variations
Shiying Xiong
EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M04/48
2004
Advisor: Jeffrey Bokor
BibTeX citation:
@phdthesis{Xiong:M04/48,
Author = {Xiong, Shiying},
Title = {Design Optimization of Ultra-Scaled Transistors and the Impact of Process Variations},
School = {EECS Department, University of California, Berkeley},
Year = {2004},
URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2004/4278.html},
Number = {UCB/ERL M04/48}
}
EndNote citation:
%0 Thesis %A Xiong, Shiying %T Design Optimization of Ultra-Scaled Transistors and the Impact of Process Variations %I EECS Department, University of California, Berkeley %D 2004 %@ UCB/ERL M04/48 %U http://www.eecs.berkeley.edu/Pubs/TechRpts/2004/4278.html %F Xiong:M04/48