# A 64-bit Partitionable Integer Multiplier for VIRAM1

### Joseph Gebis

###
EECS Department

University of California, Berkeley

Technical Report No. UCB/CSD-03-1288

November 2003

### http://www.eecs.berkeley.edu/Pubs/TechRpts/2003/CSD-03-1288.pdf

VIRAM1 (Vector Intelligent RAM 1) is a low-power multimedia processor with embedded DRAM designed at UC Berkeley in 2002 and fabricated in 2003. It includes a scalar core and four vector computation units, called lanes. The goals of the chip, low-power media processing, require that the vector lanes have efficient integer multipliers that can work with a variety of data sizes. In this report, I describe an efficient partitionable integer multiplier that is designed to work in VIRAM1's vector computation lanes. The multiplier is capable of operating with a latency of two cycles at 200 MHz in a 1.2 V, .18 micron process at 64, 32, or 16 bit data width sizes, while consuming less than 250 mW of power. I describe and evaluate design options for different parts of the multiplier, and analyze the results of the chosen options.

BibTeX citation:

@techreport{Gebis:CSD-03-1288, Author = {Gebis, Joseph}, Title = {A 64-bit Partitionable Integer Multiplier for VIRAM1}, Institution = {EECS Department, University of California, Berkeley}, Year = {2003}, Month = {Nov}, URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2003/5698.html}, Number = {UCB/CSD-03-1288}, Abstract = {VIRAM1 (Vector Intelligent RAM 1) is a low-power multimedia processor with embedded DRAM designed at UC Berkeley in 2002 and fabricated in 2003. It includes a scalar core and four vector computation units, called lanes. The goals of the chip, low-power media processing, require that the vector lanes have efficient integer multipliers that can work with a variety of data sizes. In this report, I describe an efficient partitionable integer multiplier that is designed to work in VIRAM1's vector computation lanes. The multiplier is capable of operating with a latency of two cycles at 200 MHz in a 1.2 V, .18 micron process at 64, 32, or 16 bit data width sizes, while consuming less than 250 mW of power. I describe and evaluate design options for different parts of the multiplier, and analyze the results of the chosen options.} }

EndNote citation:

%0 Report %A Gebis, Joseph %T A 64-bit Partitionable Integer Multiplier for VIRAM1 %I EECS Department, University of California, Berkeley %D 2003 %@ UCB/CSD-03-1288 %U http://www.eecs.berkeley.edu/Pubs/TechRpts/2003/5698.html %F Gebis:CSD-03-1288