High Throughput VLSI Architectures for Iterative Decoders

Engling Yeo

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M03/39
2003

Advisor: Borivoje Nikolic


BibTeX citation:

@phdthesis{Yeo:M03/39,
    Author = {Yeo, Engling},
    Title = {High Throughput VLSI Architectures for Iterative Decoders},
    School = {EECS Department, University of California, Berkeley},
    Year = {2003},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2003/4167.html},
    Number = {UCB/ERL M03/39}
}

EndNote citation:

%0 Thesis
%A Yeo, Engling
%T High Throughput VLSI Architectures for Iterative Decoders
%I EECS Department, University of California, Berkeley
%D 2003
%@ UCB/ERL M03/39
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2003/4167.html
%F Yeo:M03/39