Igor Polishchuk
EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M02/19
June 2002
http://www2.eecs.berkeley.edu/Pubs/TechRpts/2002/ERL-02-19.pdf
Advisor: Chenming Hu
BibTeX citation:
@phdthesis{Polishchuk:M02/19, Author = {Polishchuk, Igor}, Title = {Gate Stack for Sub-50nm CMOS Devices: Materials, Engineering, and Modeling}, School = {EECS Department, University of California, Berkeley}, Year = {2002}, Month = {Jun}, URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2002/3990.html}, Number = {UCB/ERL M02/19} }
EndNote citation:
%0 Thesis %A Polishchuk, Igor %T Gate Stack for Sub-50nm CMOS Devices: Materials, Engineering, and Modeling %I EECS Department, University of California, Berkeley %D 2002 %@ UCB/ERL M02/19 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2002/3990.html %F Polishchuk:M02/19