Iakovos Mavroidis

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-01-1145
May 2001

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2001/CSD-01-1145.pdf

Vector IRAM integrates vector processing with embedded DRAM on a single chip to provide high multimedia performance at low energy cost. This report presents the design and the implementation of the VIRAM Vector Register File. Our design successfully faces many challenges such as the need for speed, low power consumption, compact design and multiported access. Using a 0.18 mu-m technology and a 1.3 Volts supply voltage, it operates at 200 MHz, consumes an average power of 330 mW and 8 mm^2 of area, and provides eight read and three write ports. A number of available CAD tools were used, including layout tools from CADENCE, extraction tools from Avant!, hspice, timemill and powermill. This report gives emphasis on implementation issues and evaluates the performance and power consumption of our design.

BibTeX citation:

@techreport{Mavroidis:CSD-01-1145,
    Author = {Mavroidis, Iakovos},
    Title = {A Low Power 200 MHz Multiported Register File for the Vector-IRAM Chip},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2001},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2001/5461.html},
    Number = {UCB/CSD-01-1145},
    Abstract = {Vector IRAM integrates vector processing with embedded DRAM on a single chip to provide high multimedia performance at low energy cost. This report presents the design and the implementation of the VIRAM Vector Register File. Our design successfully faces many challenges such as the need for speed, low power consumption, compact design and multiported access. Using a 0.18 mu-m technology and a 1.3 Volts supply voltage, it operates at 200 MHz, consumes an average power of 330 mW and 8 mm^2 of area, and provides eight read and three write ports. A number of available CAD tools were used, including layout tools from CADENCE, extraction tools from Avant!, hspice, timemill and powermill. This report gives emphasis on implementation issues and evaluates the performance and power consumption of our design.}
}

EndNote citation:

%0 Report
%A Mavroidis, Iakovos
%T A Low Power 200 MHz Multiported Register File for the Vector-IRAM Chip
%I EECS Department, University of California, Berkeley
%D 2001
%@ UCB/CSD-01-1145
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2001/5461.html
%F Mavroidis:CSD-01-1145