Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

The IRAM Network Interface

Ioannis Mavroidis

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-00-1111
September 2000

http://www.eecs.berkeley.edu/Pubs/TechRpts/2000/CSD-00-1111.pdf

Vector IRAM (VIRAM) integrates vector processing with embedded DRAM technology on the same chip to provide high multimedia performance at low energy consumption. This level of integration makes VIRAM an attractive candidate as a building block for a high density multi-processor system. One node in such a system would consist of its own processor, main memory and network interface, all tightly coupled on the same chip. This report presents the design and architecture of a Network Interface targeted to a small-scale system consisting of a few VIRAM chips connected on one board. Each chip communicates using 4 narrow point-to-point bidirectional links that provide an aggregate peak throughput of over 4 Gbps per direction. The proposed Network Interface was entirely implemented and simulated in Verilog. We evaluate its performance under various communication patterns, including hot-spot and all-to-all communication. We also discuss its weaknesses and propose ways to overcome them.


BibTeX citation:

@techreport{Mavroidis:CSD-00-1111,
    Author = {Mavroidis, Ioannis},
    Title = {The IRAM Network Interface},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2000},
    Month = {Sep},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2000/5794.html},
    Number = {UCB/CSD-00-1111},
    Abstract = {Vector IRAM (VIRAM) integrates vector processing with embedded DRAM technology on the same chip to provide high multimedia performance at low energy consumption. This level of integration makes VIRAM an attractive candidate as a building block for a high density multi-processor system. One node in such a system would consist of its own processor, main memory and network interface, all tightly coupled on the same chip. This report presents the design and architecture of a Network Interface targeted to a small-scale system consisting of a few VIRAM chips connected on one board. Each chip communicates using 4 narrow point-to-point bidirectional links that provide an aggregate peak throughput of over 4 Gbps per direction. The proposed Network Interface was entirely implemented and simulated in Verilog. We evaluate its performance under various communication patterns, including hot-spot and all-to-all communication. We also discuss its weaknesses and propose ways to overcome them.}
}

EndNote citation:

%0 Report
%A Mavroidis, Ioannis
%T The IRAM Network Interface
%I EECS Department, University of California, Berkeley
%D 2000
%@ UCB/CSD-00-1111
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2000/5794.html
%F Mavroidis:CSD-00-1111