Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

The Pool of Subsectors Cache Design

Jeffrey B. Rothman and Alan Jay Smith

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-99-1035
January 1999

http://www.eecs.berkeley.edu/Pubs/TechRpts/1999/CSD-99-1035.pdf

Sector caches use an address tag to identify a sector, and valid bits to indicate whether each subsector is present in the cache. This design permits a small number of tag bits to control a large number of data bytes in the cache. Such a design is useful for single level caches when cache sizes are small and/or when the optimal line sizes are small. Sector caches are most useful when small first-level tag arrays are used to control large second level cache data arrays. The problem with sector caches is that because of the constrained mapping between address tags and data array space, frequently many of the subsectors are not filled before the sector is replaced.

In this paper, we propose a new design, called the sector pool cache, in which subsectors may be shared between sectors, so that the cache data arrays are used much more efficiently. We evaluate this design using a large multiprogrammed workload to provide a more realistic test of the various cache designs. Our results show that the sector pool cache can be an attractive solution for a first level on-chip cache when used in conjunction with a regular second level off-chip sector cache. Such a design provides improved performance by allowing a larger fraction of first level cache bits to be used for data rather than for tags.


BibTeX citation:

@techreport{Rothman:CSD-99-1035,
    Author = {Rothman, Jeffrey B. and Smith, Alan Jay},
    Title = {The Pool of Subsectors Cache Design},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1999},
    Month = {Jan},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1999/5428.html},
    Number = {UCB/CSD-99-1035},
    Abstract = {Sector caches use an address tag to identify a sector, and valid bits to indicate whether each subsector is present in the cache. This design permits a small number of tag bits to control a large number of data bytes in the cache. Such a design is useful for single level caches when cache sizes are small and/or when the optimal line sizes are small. Sector caches are most useful when small first-level tag arrays are used to control large second level cache data arrays. The problem with sector caches is that because of the constrained mapping between address tags and data array space, frequently many of the subsectors are not filled before the sector is replaced. <p>In this paper, we propose a new design, called the sector pool cache, in which subsectors may be shared between sectors, so that the cache data arrays are used much more efficiently. We evaluate this design using a large multiprogrammed workload to provide a more realistic test of the various cache designs. Our results show that the sector pool cache can be an attractive solution for a first level on-chip cache when used in conjunction with a regular second level off-chip sector cache. Such a design provides improved performance by allowing a larger fraction of first level cache bits to be used for data rather than for tags.}
}

EndNote citation:

%0 Report
%A Rothman, Jeffrey B.
%A Smith, Alan Jay
%T The Pool of Subsectors Cache Design
%I EECS Department, University of California, Berkeley
%D 1999
%@ UCB/CSD-99-1035
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1999/5428.html
%F Rothman:CSD-99-1035