Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Implementation Issues in Modern Cache Memory

Jih-Kwon Peir, Windsor W. Hsu and Alan Jay Smith

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-98-1023
November 1998

http://www.eecs.berkeley.edu/Pubs/TechRpts/1998/CSD-98-1023.pdf

As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. In this paper, we consider some of the issues that are involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets and constraints of modern processors. In particular, we consider techniques that enable the cache to be accessed quickly and still achieve a good hit ratio. We also consider issues such as area cost and bandwidth requirements. Trace-driven simulations of a TPC-C-like workload and selected applications from the SPEC95 benchmark suite are used in the paper to compare the performance of some of the techniques.


BibTeX citation:

@techreport{Peir:CSD-98-1023,
    Author = {Peir, Jih-Kwon and Hsu, Windsor W. and Smith, Alan Jay},
    Title = {Implementation Issues in Modern Cache Memory},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1998},
    Month = {Nov},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1998/5679.html},
    Number = {UCB/CSD-98-1023},
    Abstract = {As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. In this paper, we consider some of the issues that are involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets and constraints of modern processors. In particular, we consider techniques that enable the cache to be accessed quickly and still achieve a good hit ratio. We also consider issues such as area cost and bandwidth requirements. Trace-driven simulations of a TPC-C-like workload and selected applications from the SPEC95 benchmark suite are used in the paper to compare the performance of some of the techniques.}
}

EndNote citation:

%0 Report
%A Peir, Jih-Kwon
%A Hsu, Windsor W.
%A Smith, Alan Jay
%T Implementation Issues in Modern Cache Memory
%I EECS Department, University of California, Berkeley
%D 1998
%@ UCB/CSD-98-1023
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1998/5679.html
%F Peir:CSD-98-1023