Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Incremental Methods for Formal Verification and Logic Synthesis

Gitanjali M. Swamy

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M96/94
1996

Advisor: Robert K. Brayton


BibTeX citation:

@phdthesis{Swamy:M96/94,
    Author = {Swamy, Gitanjali M.},
    Title = {Incremental Methods for Formal Verification and Logic Synthesis},
    School = {EECS Department, University of California, Berkeley},
    Year = {1996},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1996/3147.html},
    Number = {UCB/ERL M96/94}
}

EndNote citation:

%0 Thesis
%A Swamy, Gitanjali M.
%T Incremental Methods for Formal Verification and Logic Synthesis
%I EECS Department, University of California, Berkeley
%D 1996
%@ UCB/ERL M96/94
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1996/3147.html
%F Swamy:M96/94