Timothy J. Callahan

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-94-823
May 1994

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1994/CSD-94-823.pdf

The overall performance of a multicomputer depends heavily on the interface between the software and the communication hardware. As pointed out in von Eicken's thesis, this communication architecture should be versatile in that it be able to support a variety of different communication models, including shared memory, dataflow, and send&receive; it should support an efficient implementation of each model; and it should be incremental in that it shouldn't interfere with the computation performance of the processor.

Active Messages communication architectures have been shown to satisfy these criteria. Software implementations of Active Messages have reduced communication overhead by over an order of magnitude to near the minimum possible given existing hardware. This project takes the next step and defines a hardware implementation of an Active Message communication architecture, resulting in another order of magnitude reduction in communication overhead.

The Active Message communication architecture defined in this report is an extension to the MIPS-II instruction set architecture. The resulting architecture features data transfer directly to/from processor registers, hardware dispatch directly to Active Message handlers (along with limited context preservation), automatic atomicity of handlers, cheap synchronization operations, and hardware support for multicast.

BibTeX citation:

@techreport{Callahan:CSD-94-823,
    Author = {Callahan, Timothy J.},
    Title = {Network Interface Specification for the T1 Microprocessor},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1994},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1994/5610.html},
    Number = {UCB/CSD-94-823},
    Abstract = {The overall performance of a multicomputer depends heavily on the interface between the software and the communication hardware. As pointed out in von Eicken's thesis, this communication architecture should be versatile in that it be able to support a variety of different communication models, including shared memory, dataflow, and send&receive; it should support an efficient implementation of each model; and it should be incremental in that it shouldn't interfere with the computation performance of the processor. <p>Active Messages communication architectures have been shown to satisfy these criteria. Software implementations of Active Messages have reduced communication overhead by over an order of magnitude to near the minimum possible given existing hardware. This project takes the next step and defines a hardware implementation of an Active Message communication architecture, resulting in another order of magnitude reduction in communication overhead. <p>The Active Message communication architecture defined in this report is an extension to the MIPS-II instruction set architecture. The resulting architecture features data transfer directly to/from processor registers, hardware dispatch directly to Active Message handlers (along with limited context preservation), automatic atomicity of handlers, cheap synchronization operations, and hardware support for multicast.}
}

EndNote citation:

%0 Report
%A Callahan, Timothy J.
%T Network Interface Specification for the T1 Microprocessor
%I EECS Department, University of California, Berkeley
%D 1994
%@ UCB/CSD-94-823
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1994/5610.html
%F Callahan:CSD-94-823