Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

High Speed Switch Scheduling for Local Area Networks

Thomas E. Anderson, Susan S. Owicki, James B. Saxe and Charles P. Thacker

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-94-803
March 1994

http://www.eecs.berkeley.edu/Pubs/TechRpts/1994/CSD-94-803.pdf

Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in fixed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram traffic. In addition, it supports real-time traffic by providing bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a technique called parallel iterative matching, which can quickly identify a set of conflict-free cells for transmission in a time slot. Bandwidth reservations are accommodated in the switch by building a fixed schedule for transporting cells from reserved flows across the switch; parallel iterative matching can fill unused slots with datagram traffic. Finally, we note that parallel iterative matching may not allocate bandwidth fairly among flows of datagram traffic. We describe a technique called statistical matching, which can be used to ensure fairness at the switch and to support applications with rapidly changing needs for guaranteed bandwidth.


BibTeX citation:

@techreport{Anderson:CSD-94-803,
    Author = {Anderson, Thomas E. and Owicki, Susan S. and Saxe, James B. and Thacker, Charles P.},
    Title = {High Speed Switch Scheduling for Local Area Networks},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1994},
    Month = {Mar},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1994/5598.html},
    Number = {UCB/CSD-94-803},
    Abstract = {Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a prototype switch for an arbitrary topology point-to-point network with link speeds of up to one gigabit per second. The switch deals in fixed-length ATM-style cells, which it can process at a rate of 37 million cells per second. It provides high bandwidth and low latency for datagram traffic. In addition, it supports real-time traffic by providing bandwidth reservations with guaranteed latency bounds. The key to the switch's operation is a technique called parallel iterative matching, which can quickly identify a set of conflict-free cells for transmission in a time slot. Bandwidth reservations are accommodated in the switch by building a fixed schedule for transporting cells from reserved flows across the switch; parallel iterative matching can fill unused slots with datagram traffic. Finally, we note that parallel iterative matching may not allocate bandwidth fairly among flows of datagram traffic. We describe a technique called statistical matching, which can be used to ensure fairness at the switch and to support applications with rapidly changing needs for guaranteed bandwidth.}
}

EndNote citation:

%0 Report
%A Anderson, Thomas E.
%A Owicki, Susan S.
%A Saxe, James B.
%A Thacker, Charles P.
%T High Speed Switch Scheduling for Local Area Networks
%I EECS Department, University of California, Berkeley
%D 1994
%@ UCB/CSD-94-803
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1994/5598.html
%F Anderson:CSD-94-803