Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

High Speed 64-b CMOS Datapath

John Wawrzynek and Bertrand Irissou

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-93-750
June 1993

http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/CSD-93-750.pdf

This paper reports on our investigations into the performance limits of CMOS datapaths. We have used a combination of single phase clocking, reduced voltage swing logic, moderate pipelining, and custom layout to achieve dramatic speed improvements over conventional design techniques. We have also used a novel fast adder structure and register file. To demonstrate the feasibility and effectiveness of these techniques and circuits, we have designed a test chip including a 64-bit integer datapath and a PLA-based finite state machine for testing. The chip layout was generated using MOSIS design rules and fabricated in the HP CMOS34 1.2-um process. It has been tested and is fully functional at 180MHZ.


BibTeX citation:

@techreport{Wawrzynek:CSD-93-750,
    Author = {Wawrzynek, John and Irissou, Bertrand},
    Title = {High Speed 64-b CMOS Datapath},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Jun},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/6305.html},
    Number = {UCB/CSD-93-750},
    Abstract = {This paper reports on our investigations into the performance limits of CMOS datapaths. We have used a combination of single phase clocking, reduced voltage swing logic, moderate pipelining, and custom layout to achieve dramatic speed improvements over conventional design techniques. We have also used a novel fast adder structure and register file. To demonstrate the feasibility and effectiveness of these techniques and circuits, we have designed a test chip including a 64-bit integer datapath and a PLA-based finite state machine for testing. The chip layout was generated using MOSIS design rules and fabricated in the HP CMOS34 1.2-um process. It has been tested and is fully functional at 180MHZ.}
}

EndNote citation:

%0 Report
%A Wawrzynek, John
%A Irissou, Bertrand
%T High Speed 64-b CMOS Datapath
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/CSD-93-750
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/6305.html
%F Wawrzynek:CSD-93-750