Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Design Techniques for High-Speed Datapaths

Bertrand S. Irissou

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-93-748
November 1992

http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/CSD-93-748.pdf

This report describes our research on the performance limits of datapaths in MOS technology. By using a combination of single-phase clocking, dynamic logic circuits, limited pipelining and custom layout, we achieve high-speed operation of the datapath and a tremendous performance increase over traditional implementations that use static CMOS circuits and multi-phase clocking. To demonstrate these techniques, we have built a 64-bit integer datapath comprising an adder, a three-ported register file and a PLA. The datapath was fabricated in the HP CMOS34 1.2um process. It has been tested and is fully functional at 180MHz.


BibTeX citation:

@techreport{Irissou:CSD-93-748,
    Author = {Irissou, Bertrand S.},
    Title = {Design Techniques for High-Speed Datapaths},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1992},
    Month = {Nov},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/6303.html},
    Number = {UCB/CSD-93-748},
    Abstract = {This report describes our research on the performance limits of datapaths in MOS technology. By using a combination of single-phase clocking, dynamic logic circuits, limited pipelining and custom layout, we achieve high-speed operation of the datapath and a tremendous performance increase over traditional implementations that use static CMOS circuits and multi-phase clocking. To demonstrate these techniques, we have built a 64-bit integer datapath comprising an adder, a three-ported register file and a PLA. The datapath was fabricated in the HP CMOS34 1.2um process. It has been tested and is fully functional at 180MHz.}
}

EndNote citation:

%0 Report
%A Irissou, Bertrand S.
%T Design Techniques for High-Speed Datapaths
%I EECS Department, University of California, Berkeley
%D 1992
%@ UCB/CSD-93-748
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/6303.html
%F Irissou:CSD-93-748