Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Measuring Cache and TLB Performance and Their Effect of Benchmark Run Times

Rafael H. Saavedra and Alan Jay Smith

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-93-767
August 1993

http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/CSD-93-767.pdf

In previous research, we have developed and presented a model for measuring machines and analyzing programs, and for accurately predicting the running time of any analyzed program on any measured machine. That work is extended here by: (a) developing a high level program to measure the design and performance of the cache and TLB for any machine; (b) using those measurements, along with published miss ratio data, to improve the accuracy of our run time predictions; (c) using our analysis tools and measurements to study and compare the design of several machines, with particular reference to their cache and TLB performance. As part of this work, we describe the design and performance of the cache and TLB for ten machines. The work presented in this paper extends a powerful technique for the evaluation and analysis of both computer systems and their workloads; this methodology is valuable both to computer users and computer system designers.


BibTeX citation:

@techreport{Saavedra:CSD-93-767,
    Author = {Saavedra, Rafael H. and Smith, Alan Jay},
    Title = {Measuring Cache and TLB Performance and Their Effect of Benchmark Run Times},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Aug},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/6283.html},
    Number = {UCB/CSD-93-767},
    Abstract = {In previous research, we have developed and presented a model for measuring machines and analyzing programs, and for accurately predicting the running time of any analyzed program on any measured machine. That work is extended here by: (a) developing a high level program to measure the design and performance of the cache and TLB for any machine; (b) using those measurements, along with published miss ratio data, to improve the accuracy of our run time predictions; (c) using our analysis tools and measurements to study and compare the design of several machines, with particular reference to their cache and TLB performance. As part of this work, we describe the design and performance of the cache and TLB for ten machines. The work presented in this paper extends a powerful technique for the evaluation and analysis of both computer systems and their workloads; this methodology is valuable both to computer users and computer system designers.}
}

EndNote citation:

%0 Report
%A Saavedra, Rafael H.
%A Smith, Alan Jay
%T Measuring Cache and TLB Performance and Their Effect of Benchmark Run Times
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/CSD-93-767
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/6283.html
%F Saavedra:CSD-93-767