Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Papyrus: A History-Based VLSI Design Process Management System

Tzi-cker Chiueh

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-93-724
January 1993

http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/CSD-93-724.pdf

With the advent of powerful computer-aided-design (CAD) tools and increasingly complicated VLSI systems, the notion of circuit design has evolved into managing complexity rather than manipulating electronic devices. Complexity arises from enormous amounts of design data as well as the complicated process of creating design data. An important observation is that modern circuit designers spend more time managing the created design data than actually running the CAD tools. The thesis of our work is: the key to further enhance VLSI designers' productivity is not better CAD tools but a more responsive infrastructure. The focus of this dissertation is thus on support mechanisms that allow composition of a set of potentially heterogeneous tools into a coherent design system, and facilitate the integration of design data and design process management.

We develop a design process support model called the Light Weight Transaction (LWT) model, which captures both the structured and exploratory aspects of VLSI design. The former corresponds to the design procedures that are well-understood and thus can be specified in advance, whereas the latter denotes the creative part of a design process. We developed a script facility to support routine design activities and proposed a history-based rework mechanism to allow interactive exploration of the design space. Unlike conventional database transaction models, the LWT model is based on a data visibility abstraction: users can operate on a piece of data only when it is visible to them. We have shown how this abstraction can support both design exploration and cooperative group work.

To demonstrate the feasibility of the LWT model, we built a prototype implementation on top of the Sprite operating system, the Tcl/Tk facility, and the Berkeley OCT CAD tool suite. This implementation features a transparent load balancing scheme to exploit the computation power of networked workstations, an atomicity-guarantee mechanism to preserve the high-level task abstraction. In addition, the rework mechanism depends on a single assignment update principle, which in turn could pose serious storage overheads. Our implementation alleviates this overhead by performing a history-based object reclamation in the background.

Based on the design operation history, we propose a novel design management paradigm: Rather than requiring users to supply design meta-data, the system maintains and analyzes the design history to deduce the metadata, in particular, object attributes and inter-object relationships, according to a suite of domain-specific knowledge and inference procedures. This paradigm can be viewed as a generalization of the approach used in syntax-directed editors. However, we believe this to be the first attempt to apply the idea in the context of design database management systems. Instead of using abstract syntax trees, we use a special representation of the design history called augmented derivation graph as the basis for design metadata inference. This paradigm opens a new way of thinking about creating information that are interesting to the system, be that a user, an operating system, or a database system.

Advisor: Randy H. Katz


BibTeX citation:

@phdthesis{Chiueh:CSD-93-724,
    Author = {Chiueh, Tzi-cker},
    Title = {Papyrus: A History-Based VLSI Design Process Management System},
    School = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Jan},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/6035.html},
    Number = {UCB/CSD-93-724},
    Abstract = {With the advent of powerful computer-aided-design (CAD) tools and increasingly complicated VLSI systems, the notion of circuit design has evolved into managing complexity rather than manipulating electronic devices. Complexity arises from enormous amounts of design data as well as the complicated process of creating design data. An important observation is that modern circuit designers spend more time managing the created design data than actually running the CAD tools. The thesis of our work is: the key to further enhance VLSI designers' productivity is not better CAD tools but a more responsive infrastructure. The focus of this dissertation is thus on support mechanisms that allow composition of a set of potentially heterogeneous tools into a coherent design system, and facilitate the integration of design data and design process management. <p>We develop a design process support model called the Light Weight Transaction (LWT) model, which captures both the structured and exploratory aspects of VLSI design. The former corresponds to the design procedures that are well-understood and thus can be specified in advance, whereas the latter denotes the creative part of a design process. We developed a script facility to support routine design activities and proposed a history-based rework mechanism to allow interactive exploration of the design space. Unlike conventional database transaction models, the LWT model is based on a data visibility abstraction: users can operate on a piece of data only when it is visible to them. We have shown how this abstraction can support both design exploration and cooperative group work. <p>To demonstrate the feasibility of the LWT model, we built a prototype implementation on top of the Sprite operating system, the Tcl/Tk facility, and the Berkeley OCT CAD tool suite. This implementation features a transparent load balancing scheme to exploit the computation power of networked workstations, an atomicity-guarantee mechanism to preserve the high-level task abstraction. In addition, the rework mechanism depends on a single assignment update principle, which in turn could pose serious storage overheads. Our implementation alleviates this overhead by performing a history-based object reclamation in the background. <p>Based on the design operation history, we propose a novel design management paradigm: Rather than requiring users to supply design meta-data, the system maintains and analyzes the design history to deduce the metadata, in particular, object attributes and inter-object relationships, according to a suite of domain-specific knowledge and inference procedures. This paradigm can be viewed as a generalization of the approach used in syntax-directed editors. However, we believe this to be the first attempt to apply the idea in the context of design database management systems. Instead of using abstract syntax trees, we use a special representation of the design history called augmented derivation graph as the basis for design metadata inference. This paradigm opens a new way of thinking about creating information that are interesting to the system, be that a user, an operating system, or a database system.}
}

EndNote citation:

%0 Thesis
%A Chiueh, Tzi-cker
%T Papyrus: A History-Based VLSI Design Process Management System
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/CSD-93-724
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/6035.html
%F Chiueh:CSD-93-724