Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Low-Power Silicon Neurons, Axons, and Synapses

John Lazzaro and John Wawrzynek

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-93-751
June 1993

http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/CSD-93-751.pdf

Power consumption is the dominant design issue for battery-powered electronic devices. Biologically-inspired sensory preprocessors may be an important component of portable computing devices that require real-world visual or auditory input. The silicon neural design style presented in (Mead, 1989; Andreou et al., 1991) naturally supports low-power VLSI design; in this design style, MOS transistors typically operate in the weak-inversion regime. The low-power performance of this design style is outstanding; for example, (Watts et al., 1991) reports on a 51-stage silicon cochlea, that computes all outputs in real time and consumes 11 muW.

However, several popular circuits in this design style operate transistors outside the weak-inversion regime. These circuits, that model the spiking behavior of the axon hillock and the pulse propagation of axons, dominate power consumption in many neural chips (Lazzaro and Mead, 1989ab; Lazzaro, 1991; Horiuchi et al., 1991).

This chapter describes modified versions of these axon circuits. The modified circuits have been designed and fabricated and are fully functional; these circuits show a measured improvement in power consumption over the original circuits. Power consumption decreases of a factor of 10 to 1000 have been measured, depending on pulse width and spiking frequency. The density of the modified circuits is comparable to the original circuits. This chapter also describes several low-power synaptic circuits.


BibTeX citation:

@techreport{Lazzaro:CSD-93-751,
    Author = {Lazzaro, John and Wawrzynek, John},
    Title = {Low-Power Silicon Neurons, Axons, and Synapses},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Jun},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/5552.html},
    Number = {UCB/CSD-93-751},
    Abstract = {Power consumption is the dominant design issue for battery-powered electronic devices. Biologically-inspired sensory preprocessors may be an important component of portable computing devices that require real-world visual or auditory input. The silicon neural design style presented in (Mead, 1989; Andreou et al., 1991) naturally supports low-power VLSI design; in this design style, MOS transistors typically operate in the weak-inversion regime. The low-power performance of this design style is outstanding; for example, (Watts et al., 1991) reports on a 51-stage silicon cochlea, that computes all outputs in real time and consumes 11 muW. <p>However, several popular circuits in this design style operate transistors outside the weak-inversion regime. These circuits, that model the spiking behavior of the axon hillock and the pulse propagation of axons, dominate power consumption in many neural chips (Lazzaro and Mead, 1989ab; Lazzaro, 1991; Horiuchi et al., 1991). <p>This chapter describes modified versions of these axon circuits. The modified circuits have been designed and fabricated and are fully functional; these circuits show a measured improvement in power consumption over the original circuits. Power consumption decreases of a factor of 10 to 1000 have been measured, depending on pulse width and spiking frequency. The density of the modified circuits is comparable to the original circuits. This chapter also describes several low-power synaptic circuits.}
}

EndNote citation:

%0 Report
%A Lazzaro, John
%A Wawrzynek, John
%T Low-Power Silicon Neurons, Axons, and Synapses
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/CSD-93-751
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/5552.html
%F Lazzaro:CSD-93-751