Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Timing Issues in Sequential Circuits

Narendra V. Shenoy

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M93/97
1993

Design automation techniques play a major role in VLSI design. Growth in the complexity of circuits and performance requirements has necessitated the use of computer aided design tools. We examine some of the problems faced in the design of high performance synchronous circuits. Synchronous circuits use complex clocking schedules and circuit structures to capture and store data signals. The performance metric is measured by the periodicity of signals in the clocking schedule. The first aspect of this thesis is devoted to the analysis of synchronous circuits. A clocking schedule must satisfy constraints that arise from the circuit topology and delay distribution on gates, wires and memory elements. Analysis to examine if a clock schedule is error-free is first considered. Improving the performance metric without changing the circuit typology the next issue considered. Flexibility in changing the clock signals and borrowing time across level-sensitive memory elements provides ample freedom for improving the circuit performance and should be exploited. The second aspect focusses on performance improvement by transforming the circuit structure. A technique to use existing combinational delay optimizers repeatedly to solve the sequential performance problem is proposed. The approach uses an innovative notion of "perturbation" to extract timing constraints. If the difference between the largest and the smallest delays of paths between a pair of memory elements is significant, the short path can cause erroneous latching of data. This is known as the short path problem. We investigate this problem and propose a solution based on active delay insertion.

Advisor: Alberto L. Sangiovanni-Vincentelli


BibTeX citation:

@phdthesis{Shenoy:M93/97,
    Author = {Shenoy, Narendra V.},
    Title = {Timing Issues in Sequential Circuits},
    School = {EECS Department, University of California, Berkeley},
    Year = {1993},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/2482.html},
    Number = {UCB/ERL M93/97},
    Abstract = {Design automation techniques play a major role in VLSI design. Growth in the complexity of circuits and performance requirements has necessitated the use of computer aided design tools.  We examine some of the problems faced in the design of high performance synchronous circuits. Synchronous circuits use complex clocking schedules and circuit structures to capture and store data signals.  The performance metric is measured by the periodicity of signals in the clocking schedule. The first aspect of this thesis is devoted to the analysis of synchronous circuits.  A clocking schedule must satisfy constraints that arise from the circuit topology and delay distribution on gates, wires and memory elements. Analysis to examine if a clock schedule is error-free is first considered. Improving the performance metric without changing the circuit typology the next issue considered.  Flexibility in changing the clock signals and borrowing time across level-sensitive memory elements provides ample freedom for improving the circuit performance and should be exploited. The second aspect focusses on performance improvement by transforming the circuit structure.  A technique to use existing combinational delay optimizers repeatedly to solve the sequential performance problem is proposed.  The approach uses an innovative notion of "perturbation" to extract timing constraints.  If the difference between the largest and the smallest delays of paths between a pair of memory elements is significant, the short path can cause erroneous latching of data.  This is known as the short path problem. We investigate this problem and propose a solution based on active delay insertion.}
}

EndNote citation:

%0 Thesis
%A Shenoy, Narendra V.
%T Timing Issues in Sequential Circuits
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/97
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1993/2482.html
%F Shenoy:M93/97