Logic Synthesis and Massively Parallel Computers: Tools for Speeding-Up Logic Simulation

G.A. Jones

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M93/16
February 1993

http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/ERL-93-16.pdf

Simulation continues to be a major tool in the design of digital circuits. With increases in design sizes and the relative simulation times, the need for better simulation performance, covering both software techniques and hardware acceleration methods. This report combines both ideas. On the software side, the concept is presented for using logic synthesis techniques to produce better implementations of a circuit for functional simulation. From a hardware perspective, this concept is investigated using a simulator running on a massively parallel SIMD computer. Synthesis tools are used to modify the functional description of a circuit to increase the parallelism and shorten the expected simulation time while mapping the description for execution on the parallel architecture.

BibTeX citation:

@techreport{Jones:M93/16,
    Author = {Jones, G.A.},
    Title = {Logic Synthesis and Massively Parallel Computers: Tools for Speeding-Up Logic Simulation},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1993},
    Month = {Feb},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2294.html},
    Number = {UCB/ERL M93/16},
    Abstract = {Simulation continues to be a major tool in the design of digital circuits. With increases in design sizes and the relative simulation times, the need for better simulation performance, covering both software techniques and hardware acceleration methods. This report combines both ideas. On the software side, the concept is presented for using logic synthesis techniques to produce better implementations of a circuit for functional simulation. From a hardware perspective, this concept is investigated using a simulator running on a massively parallel SIMD computer. Synthesis tools are used to modify the functional description of a circuit to increase the parallelism and shorten the expected simulation time while mapping the description for execution on the parallel architecture.}
}

EndNote citation:

%0 Report
%A Jones, G.A.
%T Logic Synthesis and Massively Parallel Computers: Tools for Speeding-Up Logic Simulation
%I EECS Department, University of California, Berkeley
%D 1993
%@ UCB/ERL M93/16
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/2294.html
%F Jones:M93/16