Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Vector Processor Caches

Jeffrey D. Gee and Alan Jay Smith

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-92-707
October 1992

http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/CSD-92-707.pdf

Vector processors have typically used vector registers, interleaved memory, and pipelined access to data to provide sufficient memory system performance. Caches have been used mainly for instructions, while data references are usually uncached, presumably partially because of the belief that there is insufficient data locality in vector workloads. In this study we use memory address traces from Cray X-MP and Ardent Titan machines to examine both reference locality and cache performance in a vector processing environment. Many of the Titan traces in particular are from real vectorized applications which reference large amounts of data. We have found that vector references contain somewhat less temporal locality, but large amounts of spatial locality compared to instruction and scalar references. Cache miss ratios are found to be comparable to those measured and published previously for various non-vectorized workloads. We provide analyses of trace behavior with regard to parameters of interest to cache designers. Calculations based on our measured miss ratios indicate that caches will improve average access times, which in turn can be expected to translate into significant improvements in machine performance.


BibTeX citation:

@techreport{Gee:CSD-92-707,
    Author = {Gee, Jeffrey D. and Smith, Alan Jay},
    Title = {Vector Processor Caches},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1992},
    Month = {Oct},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/6251.html},
    Number = {UCB/CSD-92-707},
    Abstract = {Vector processors have typically used vector registers, interleaved memory, and pipelined access to data to provide sufficient memory system performance. Caches have been used mainly for instructions, while data references are usually uncached, presumably partially because of the belief that there is insufficient data locality in vector workloads. In this study we use memory address traces from Cray X-MP and Ardent Titan machines to examine both reference locality and cache performance in a vector processing environment. Many of the Titan traces in particular are from real vectorized applications which reference large amounts of data. We have found that vector references contain somewhat less temporal locality, but large amounts of spatial locality compared to instruction and scalar references. Cache miss ratios are found to be comparable to those measured and published previously for various non-vectorized workloads. We provide analyses of trace behavior with regard to parameters of interest to cache designers. Calculations based on our measured miss ratios indicate that caches will improve average access times, which in turn can be expected to translate into significant improvements in machine performance.}
}

EndNote citation:

%0 Report
%A Gee, Jeffrey D.
%A Smith, Alan Jay
%T Vector Processor Caches
%I EECS Department, University of California, Berkeley
%D 1992
%@ UCB/CSD-92-707
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/6251.html
%F Gee:CSD-92-707