Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Designing Synchronous Algorithms for Asynchronous Processors

Ramesh Subramonian

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-92-674
March 1992

http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/CSD-92-674.pdf

The PRAM model has proven to be a fertile ground for algorithm development. However, it assumes that processors operate synchronously, whereas most shared-memory multiprocessors are asynchronous and are likely to remain so. This has motivated the development of simulations of PRAM programs on asynchronous PRAMs. However, such simulations induce either a time or work penalty.

Avoiding this penalty has meant designing specifically asynchronous algorithms. To date, the design of these asynchronous algorithms has been ad-hoc and non-intuitive. We show how many algorithms, designed and analyzed assuming synchrony, can be easily and systematically converted so that the same work and time bounds are maintained under arbitrary asynchrony. The existence of lower bounds indicates that there exist problems for which the same work and time bounds cannot be maintained. However, this paper shows that in far more cases than hitherto thought possible, asynchrony does not induce a time or work penalty.

We suggest a radically new approach to the problem of cache coherence. We show how appropriate architectural support motivates the design of algorithms which are immune to cache incoherence.


BibTeX citation:

@techreport{Subramonian:CSD-92-674,
    Author = {Subramonian, Ramesh},
    Title = {Designing Synchronous Algorithms for Asynchronous Processors},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1992},
    Month = {Mar},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/6132.html},
    Number = {UCB/CSD-92-674},
    Abstract = {The PRAM model has proven to be a fertile ground for algorithm development. However, it assumes that processors operate synchronously, whereas most shared-memory multiprocessors are asynchronous and are likely to remain so. This has motivated the development of simulations of PRAM programs on asynchronous PRAMs. However, such simulations induce either a time or work penalty. <p>Avoiding this penalty has meant designing specifically asynchronous algorithms. To date, the design of these asynchronous algorithms has been ad-hoc and non-intuitive. We show how many algorithms, designed and analyzed assuming synchrony, can be easily and systematically converted so that the same work and time bounds are maintained under arbitrary asynchrony. The existence of lower bounds indicates that there exist problems for which the same work and time bounds cannot be maintained. However, this paper shows that in far more cases than hitherto thought possible, asynchrony does not induce a time or work penalty. <p>We suggest a radically new approach to the problem of cache coherence. We show how appropriate architectural support motivates the design of algorithms which are immune to cache incoherence.}
}

EndNote citation:

%0 Report
%A Subramonian, Ramesh
%T Designing Synchronous Algorithms for Asynchronous Processors
%I EECS Department, University of California, Berkeley
%D 1992
%@ UCB/CSD-92-674
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/6132.html
%F Subramonian:CSD-92-674