Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Formal Verification of Timing Constrained Finite-State Systems

F. Balarin and Alberto L. Sangiovanni-Vincentelli

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M92/8
1992

:wq


BibTeX citation:

@techreport{Balarin:M92/8,
    Author = {Balarin, F. and Sangiovanni-Vincentelli, Alberto L.},
    Title = {Formal Verification of Timing Constrained Finite-State Systems},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1992},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/1940.html},
    Number = {UCB/ERL M92/8},
    Abstract = {:wq}
}

EndNote citation:

%0 Report
%A Balarin, F.
%A Sangiovanni-Vincentelli, Alberto L.
%T Formal Verification of Timing Constrained Finite-State Systems
%I EECS Department, University of California, Berkeley
%D 1992
%@ UCB/ERL M92/8
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/1940.html
%F Balarin:M92/8