Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine

David E. Culler, Anurug Soh, Klaus Erik Schauser, Thorsten von Eicken and John Wawrzynek

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-90-594
April 1991

http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/CSD-90-594.pdf

In this paper, we present a relatively primitive execution model for fine-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is defined by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for effective register use under quasi-dynamic scheduling.

A prototype TAM instruction set, TL0, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring fine-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors.

Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such as proposed dataflow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specific hardware support or merely an appropriate compilation strategy and program representation.


BibTeX citation:

@techreport{Culler:CSD-90-594,
    Author = {Culler, David E. and Soh, Anurug and Schauser, Klaus Erik and von Eicken, Thorsten and Wawrzynek, John},
    Title = {Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1991},
    Month = {Apr},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1991/6383.html},
    Number = {UCB/CSD-90-594},
    Abstract = {In this paper, we present a relatively primitive execution model for fine-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is defined by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for effective register use under quasi-dynamic scheduling. <p>A prototype TAM instruction set, TL0, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring fine-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors. <p>Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such as proposed dataflow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specific hardware support or merely an appropriate compilation strategy and program representation.}
}

EndNote citation:

%0 Report
%A Culler, David E.
%A Soh, Anurug
%A Schauser, Klaus Erik
%A von Eicken, Thorsten
%A Wawrzynek, John
%T Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine
%I EECS Department, University of California, Berkeley
%D 1991
%@ UCB/CSD-90-594
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1991/6383.html
%F Culler:CSD-90-594