Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Modeling and Simulation of Hot-Carrier Effects in MOS Devices and Circuits

Peter M. Lee

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M90/30
1990

The dissertation presents a hot-carrier reliability simulator called BERT-CAS which can predict circuit performance degradation using device-level quasi-static models, starting from a parametric substrate current model and extending to the calculation of "aged" model parameters for transistors undergoing dynamic operation within a circuit. By using CAS, circuit designers can not only predict the degraded behavior of their circuits, but can also study which devices in the circuit experience the greatest degradation and which have the most effect to circuit output. Alternative circuit experience the greatest degradation and which have the most effect to circuit output. Alternative circuit designs can be evaluated, and thus circuits more robust to hot-carrier effects can be designed. >From CAS simulations and experimental results (reported elsewhere and in this dissertation) it is found that device degradation correlates better with the degradation driving force Ids(Isub/Ids)m rather than with Isub alone. Because CAS is based on the full degradation model rather than just Isub, accurate prediction is achieved. In general, a simulator such as CAS is necessary to predict circuit hot-carrier degradation from device-level concepts. However, for the special case of CMOS inverter-based circuits, a rough rule of thumb has been developed for quick estimation of circuit degradation from device-level stress tests. A bipolar charge-storage phenomenon causing an extended substrate current flow is also presented. When a NMOSFET used as the driver device in an inverter enters the avalanche breakdown regime of operation during an input low-to-high transient, a substantial amount of charge is seen to be generated as far as 20um away from the transistor, with a subsequent long substrate current flow to drain the excess charge. This phenomenon can thus have adverse effects to neighboring structures. Device simulation results using a three-dimensional two-carrier simulator (CADDETH) arc presented to study the phenomenon and to show its effects on CMOS latchup. This phenomenon also explains the fact that dynamic periodic inverter-based circuits can tolerate power supply voltages greater than the avalanche breakdown voltage of the individual devices, as long as the signal frequency is low enough.

Advisor: Ping K. Ko


BibTeX citation:

@phdthesis{Lee:M90/30,
    Author = {Lee, Peter M.},
    Title = {Modeling and Simulation of Hot-Carrier Effects in MOS Devices and Circuits},
    School = {EECS Department, University of California, Berkeley},
    Year = {1990},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/1460.html},
    Number = {UCB/ERL M90/30},
    Abstract = {The dissertation presents a hot-carrier reliability simulator called BERT-CAS which can predict circuit performance degradation using device-level quasi-static models, starting from a parametric substrate current model and extending to the calculation of "aged" model parameters for transistors undergoing dynamic operation within a circuit.  By using CAS, circuit designers can not only predict the degraded behavior of their circuits, but can also study which devices in the circuit experience the greatest degradation and which have the most effect to circuit output.  Alternative circuit experience the greatest degradation and which have the most effect to circuit output.  Alternative circuit designs can be evaluated, and thus circuits more robust to hot-carrier effects can be designed. >From CAS simulations and experimental results (reported elsewhere and in this dissertation) it is found that device degradation correlates better with the degradation driving force Ids(Isub/Ids)m rather than with Isub alone.  Because CAS is based on the full degradation model rather than just Isub, accurate prediction is achieved. In general, a simulator such as CAS is necessary to predict circuit hot-carrier degradation from device-level concepts.  However, for the special case of CMOS inverter-based circuits, a rough rule of thumb has been developed for quick estimation of circuit degradation from device-level stress tests. A bipolar charge-storage phenomenon causing an extended substrate current flow is also presented.  When a NMOSFET used as the driver device in an inverter enters the avalanche breakdown regime of operation during an input low-to-high transient, a substantial amount of charge is seen to be generated as far as 20um away from the transistor, with a subsequent long substrate current flow to drain the excess charge.  This phenomenon can thus have adverse effects to neighboring structures.  Device simulation results using a three-dimensional two-carrier simulator (CADDETH) arc presented to study the phenomenon and to show its effects on CMOS latchup.  This phenomenon also explains the fact that dynamic periodic inverter-based circuits can tolerate power supply voltages greater than the avalanche breakdown voltage of the individual devices, as long as the signal frequency is low enough.}
}

EndNote citation:

%0 Thesis
%A Lee, Peter M.
%T Modeling and Simulation of Hot-Carrier Effects in MOS Devices and Circuits
%I EECS Department, University of California, Berkeley
%D 1990
%@ UCB/ERL M90/30
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/1460.html
%F Lee:M90/30