Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Multiple-Output Shared Transistor Logic (MOSTL) Family Synthesized Using Binary Decision Diagram

T. Sakurai, B. Lin and A. Richard Newton

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M90/21
1990

A new type of logic family, Multiple-Output Shared Transistor Logic (MOSTL) family, is defined and a synthesis method for generating MOSTL is described. The MOSTL implements a logic function not by combining logic gates such as NAND's and OR's, but by combining transistors directly as switches. Since the MOSTL has more freedom in realizing a logic function, it offers a smaller and faster circuit than the standard cell based approach. More concretely speaking, in the MOSTL, transistors are shared among several logic functions and thus the number of MOSFET's are reduced and this in turn may reduce delay time. It is best suited for the Sea-Of-Gates designs and a full manual design where designers are permitted to build a circuit at a transistor level. A synthesis method presented is based on Binary Decision Diagram (BDD) and usually gives a good solution. The method is demonstrated to generate a sneak-path free circuit and in this sense never fails to produce a solution, which is an important feature when applied to real designs. A MOSTL together with the synthesis method will provide a systematic way to generate a 'clever' circuit, which could only have been built by the ingenuity of experienced circuit designers otherwise.


BibTeX citation:

@techreport{Sakurai:M90/21,
    Author = {Sakurai, T. and Lin, B. and Newton, A. Richard},
    Title = {Multiple-Output Shared Transistor Logic (MOSTL) Family Synthesized Using Binary Decision Diagram},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1990},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/1433.html},
    Number = {UCB/ERL M90/21},
    Abstract = {A new type of logic family, Multiple-Output Shared Transistor Logic (MOSTL) family, is defined and a synthesis method for generating MOSTL is described. The MOSTL implements a logic function not by combining logic gates such as NAND's and OR's, but by combining transistors directly as switches. Since the MOSTL has more freedom in realizing a logic function, it offers a smaller and faster circuit than the standard cell based approach.  More concretely speaking, in the MOSTL, transistors are shared among several logic functions and thus the number of MOSFET's are reduced and this in turn may reduce delay time.  It is best suited for the Sea-Of-Gates designs and a full manual design where designers are permitted to build a circuit at a transistor level. A synthesis method presented is based on Binary Decision Diagram (BDD) and usually gives a good solution.  The method is demonstrated to generate a sneak-path free circuit and in this sense never fails to produce a solution, which is an important feature when applied to real designs. A MOSTL together with the synthesis method will provide a systematic way to generate a 'clever' circuit, which could only have been built by the ingenuity of experienced circuit designers otherwise.}
}

EndNote citation:

%0 Report
%A Sakurai, T.
%A Lin, B.
%A Newton, A. Richard
%T Multiple-Output Shared Transistor Logic (MOSTL) Family Synthesized Using Binary Decision Diagram
%I EECS Department, University of California, Berkeley
%D 1990
%@ UCB/ERL M90/21
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1990/1433.html
%F Sakurai:M90/21