Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

The SPUR CPU Behavioral Model

Shing Kong

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-89-508
May 1989

The SPUR CPU is a third-generation RISC microprocessor developed at U. C. Berkeley. It is implemented using 115,000 transistors in a 1.6 um double-layer metal CMOS technology. Clock frequency is 10 MHz and power consumption is 0.8 W. Important features of the SPUR CPU are: an internal instruction cache, a four-stage pipeline, support for LISP, a cache controller interface for multiprocessing and virtual memory support, and a parallel coprocessor interface for floating point arithmetic support. These features make the SPUR CPU significantly different and more complex than previous Berkeley RISC machines, RISC I, RISC II and SOAR. More importantly, the SPUR CPU is a major building block for the SPUR multiprocessor workstation. All these require the SPUR CPU to be simulated extensively at the behavioral level. This report documents the behavioral model of the SPUR CPU that were used for behavioral simulation.


BibTeX citation:

@techreport{Kong:CSD-89-508,
    Author = {Kong, Shing},
    Title = {The SPUR CPU Behavioral Model},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1989},
    Month = {May},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/6156.html},
    Number = {UCB/CSD-89-508},
    Abstract = {The SPUR CPU is a third-generation RISC microprocessor developed at U. C. Berkeley. It is implemented using 115,000 transistors in a 1.6 um double-layer metal CMOS technology. Clock frequency is 10 MHz and power consumption is 0.8 W. Important features of the SPUR CPU are: an internal instruction cache, a four-stage pipeline, support for LISP, a cache controller interface for multiprocessing and virtual memory support, and a parallel coprocessor interface for floating point arithmetic support. These features make the SPUR CPU significantly different and more complex than previous Berkeley RISC machines, RISC I, RISC II and SOAR. More importantly, the SPUR CPU is a major building block for the SPUR multiprocessor workstation. All these require the SPUR CPU to be simulated extensively at the behavioral level. This report documents the behavioral model of the SPUR CPU that were used for behavioral simulation.}
}

EndNote citation:

%0 Report
%A Kong, Shing
%T The SPUR CPU Behavioral Model
%I EECS Department, University of California, Berkeley
%D 1989
%@ UCB/CSD-89-508
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/6156.html
%F Kong:CSD-89-508