Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Task Specification and Management in the VLSI Design Process

Valerie D. King

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-89-533
September 1989

http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/CSD-89-533.pdf

Task specification and management is presented as one aspect of a complete model for managing the VLSI design process. I describe the appropriate role of tasks in the design process, their hierarchical specification, including a detailed description of the grammar used, how they are invoked, and then present a prototype implementation integrated into the U. C. Berkeley CAD environment. The task management model presented includes a Template Manager for handling static operations on task specifications, called templates, and a Tool Navigator for dynamic operations including running, previewing, suspending, and resuming tasks.


BibTeX citation:

@techreport{King:CSD-89-533,
    Author = {King, Valerie D.},
    Title = {Task Specification and Management in the VLSI Design Process},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1989},
    Month = {Sep},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/5911.html},
    Number = {UCB/CSD-89-533},
    Abstract = {Task specification and management is presented as one aspect of a complete model for managing the VLSI design process. I describe the appropriate role of tasks in the design process, their hierarchical specification, including a detailed description of the grammar used, how they are invoked, and then present a prototype implementation integrated into the U. C. Berkeley CAD environment. The task management model presented includes a Template Manager for handling static operations on task specifications, called templates, and a Tool Navigator for dynamic operations including running, previewing, suspending, and resuming tasks.}
}

EndNote citation:

%0 Report
%A King, Valerie D.
%T Task Specification and Management in the VLSI Design Process
%I EECS Department, University of California, Berkeley
%D 1989
%@ UCB/CSD-89-533
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/5911.html
%F King:CSD-89-533