Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Managing the VLSI Design Process

Tzi-cker F. Chiueh, Randy H. Katz and Valerie D. King

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-89-538
November 1989

http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/CSD-89-538.pdf

Ways to represent and structure data within the design environment are reasonably well-understood, and have led to a number of proposed and implemented design frameworks. Comparable support for the operational nature of design, i.e., the controlled and disciplined sequencing of CAD tool invocations, are still in their infancy. In this paper, we describe a model for managing designers' work within the VLSI design environment. The model is based on a task specification language, for encapsulating CAD tool invocations and arranging the sequencing of such invocations to accomplish specific tasks, and an activity/history model, which maintains the history of task invocations and serves as a focus for sharing work results in a cooperative manner. The task specification language and a prototype tool navigator have been implemented within the OCT CAD framework.

Key words and phrases: design databases, process management, groupware, task specification, activity model


BibTeX citation:

@techreport{Chiueh:CSD-89-538,
    Author = {Chiueh, Tzi-cker F. and Katz, Randy H. and King, Valerie D.},
    Title = {Managing the VLSI Design Process},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1989},
    Month = {Nov},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/5900.html},
    Number = {UCB/CSD-89-538},
    Abstract = {Ways to represent and structure data within the design environment are reasonably well-understood, and have led to a number of proposed and implemented design frameworks. Comparable support for the operational nature of design, i.e., the controlled and disciplined sequencing of CAD tool invocations, are still in their infancy. In this paper, we describe a model for managing designers' work within the VLSI design environment. The model is based on a task specification language, for encapsulating CAD tool invocations and arranging the sequencing of such invocations to accomplish specific tasks, and an activity/history model, which maintains the history of task invocations and serves as a focus for sharing work results in a cooperative manner. The task specification language and a prototype tool navigator have been implemented within the OCT CAD framework.  <p>Key words and phrases: design databases, process management, groupware, task specification, activity model}
}

EndNote citation:

%0 Report
%A Chiueh, Tzi-cker F.
%A Katz, Randy H.
%A King, Valerie D.
%T Managing the VLSI Design Process
%I EECS Department, University of California, Berkeley
%D 1989
%@ UCB/CSD-89-538
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/5900.html
%F Chiueh:CSD-89-538