Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Extraction of Topography Dependent Electrical Characteristics From Process Simulation Using SIMPL, with Application to Planarization and Dense Interconnect Technologies

Edward W. Scheckler

EECS Department
University of California, Berkeley
Technical Report No. UCB/ERL M89/72
1989

http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/ERL-89-72.pdf

This project demonstrates the use of SIMPL-2 (SIMulated Profiles from the Layout) and SIMPL-DIX (Design interface with X windows) as an interface to other process and device simulators. An interface to RACPLE for analyzing topography dependent parasitic resistances and capacitances is implemented. Enhancements to SIMPL to call the non-planar etch simulation capabilities of SAMPLE are also presented. These integrated CAD tools are applied to a patterned photoresist planarization process, and to VLSI Hopfield neural networks. It is found that the patterned photoresist planarization process shows a relatively high tolerance to reasonable misalignments. VLSI neural networks show significant topography dependent RC parasitic delays which increase as the square of the number of neurons. Based on experience gained as a result of this work, several suggestions for the future of SIMPL are offered.


BibTeX citation:

@techreport{Scheckler:M89/72,
    Author = {Scheckler, Edward W.},
    Title = {Extraction of Topography Dependent Electrical Characteristics From Process Simulation Using SIMPL, with Application to Planarization and Dense Interconnect Technologies},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1989},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/1260.html},
    Number = {UCB/ERL M89/72},
    Abstract = {This project demonstrates the use of SIMPL-2 (SIMulated Profiles
from the Layout) and SIMPL-DIX (Design interface with X windows)
as an interface to other process and device simulators. An 
interface to RACPLE for analyzing topography dependent parasitic
resistances and capacitances is implemented. Enhancements to SIMPL to
call the non-planar etch simulation capabilities of SAMPLE are also
presented. These integrated CAD tools are applied to a patterned
photoresist planarization process, and to VLSI Hopfield neural
networks. It is found that the patterned photoresist planarization
process shows a relatively high tolerance to reasonable
misalignments. VLSI neural networks show significant topography
dependent RC parasitic delays which increase as the square of the
number of neurons. Based on experience gained as a result of this
work, several suggestions for the future of SIMPL are offered.}
}

EndNote citation:

%0 Report
%A Scheckler, Edward W.
%T Extraction of Topography Dependent Electrical Characteristics From Process Simulation Using SIMPL, with Application to Planarization and Dense Interconnect Technologies
%I EECS Department, University of California, Berkeley
%D 1989
%@ UCB/ERL M89/72
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1989/1260.html
%F Scheckler:M89/72