Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

VLSI Design Techniques for Floating-Point Computation

Bidyut Kumar Bose

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-88-469
November 1988

http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/CSD-88-469.pdf

This thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed into two micron CMOS for SPUR are described, including special design considerations for very wide datapaths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

Advisor: David A. Patterson


BibTeX citation:

@phdthesis{Bose:CSD-88-469,
    Author = {Bose, Bidyut Kumar},
    Title = {VLSI Design Techniques for Floating-Point Computation},
    School = {EECS Department, University of California, Berkeley},
    Year = {1988},
    Month = {Nov},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/6059.html},
    Number = {UCB/CSD-88-469},
    Abstract = {This thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed into two micron CMOS for SPUR are described, including special design considerations for very wide datapaths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.}
}

EndNote citation:

%0 Thesis
%A Bose, Bidyut Kumar
%T VLSI Design Techniques for Floating-Point Computation
%I EECS Department, University of California, Berkeley
%D 1988
%@ UCB/CSD-88-469
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/6059.html
%F Bose:CSD-88-469