Robert Yung

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-88-418
May 1988

The purpose of the Aquarius Project conducted at the University of California, Berkeley is to investigate new approaches to achieve high performance in numeric and symbolic calculations. The objective of the Aquarius Numeric Processor (ANP) is to provide an extended Instruction Set Architecture (ISA) for the Berkeley Programmed Logic Machine (PLM) symbolic processor (of the Aquarius Project) to allow efficient execution of symbolic and numeric programs written in AI languages such as Prolog and Lisp. The design goals of this project were:

1) Define an extended set of numeric data types and instructions to the PLM. New data types should conform to the IEEE Standard 754 which includes integer, single and double precision floating point numbers. All data types should be provided in scalar and vector (array) forms.

2) Extend the syntactic and semantic definitions of some Prolog predicates for the new data types.

3) Develop an execution and programmer model for an embedded symbolic and numeric system based on the ANP/PLM.

4) Design a tightly-coupled co-processor interface protocol between ANP and PLM to achieve high overall system performance with minimal duplication of functionality.

5) Design a hardware implementation of the ANP according to the extended ISA with minimal microarchitectural and hardware changes to the existing PLM system.

6) Increase the overall system performance for numeric intensive programs by an order of magnitude with the addition of the ANP co-processor.

7) Develop a high performance math library to support frequently used operations based on the ANP/PLM architecture.

The processor is divided into five major functional units. The Bus Interface Unit (BIU) implements that co-processor interface protocol between ANP, PLM and the memory system. The Operand Coercion Unit (OCU) coerces mismatched data types and manages operands' vector length. The Execution Unit (EU), based on the Bipolar Integrated Technology (BIT) numeric chip set, is the numeric data path in the ANP. The scalar and vector Storage Unit (SU) consists of high speed multi-port register files which keep the Execution Unit at its maximum throughput. The writable control store, micro-sequencer and exception handling logic are located in the Micro Control Unit (MCU).

The ANP is currently being built using high speed TTL and ECL parts. This dissertation covers the design and simulation of the ANP and the evaluation of the ANP/PLM system using simulated execution of some modified Whetstone and Linpack benchmark programs.

BibTeX citation:

@techreport{Yung:CSD-88-418,
    Author = {Yung, Robert},
    Title = {The Aquarius Numeric Processor},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1988},
    Month = {May},
    URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/6038.html},
    Number = {UCB/CSD-88-418},
    Abstract = {The purpose of the Aquarius Project conducted at the University of California, Berkeley is to investigate new approaches to achieve high performance in numeric and symbolic calculations. The objective of the Aquarius Numeric Processor (ANP) is to provide an extended Instruction Set Architecture (ISA) for the Berkeley Programmed Logic Machine (PLM) symbolic processor (of the Aquarius Project) to allow efficient execution of symbolic and numeric programs written in AI languages such as Prolog and Lisp. The design goals of this project were: <p> 1) Define an extended set of numeric data types and instructions to the PLM. New data types should conform to the IEEE Standard 754 which includes integer, single and double precision floating point numbers. All data types should be provided in scalar and vector (array) forms. <p> 2) Extend the syntactic and semantic definitions of some Prolog predicates for the new data types. <p> 3) Develop an execution and programmer model for an embedded symbolic and numeric system based on the ANP/PLM. <p> 4) Design a tightly-coupled co-processor interface protocol between ANP and PLM to achieve high overall system performance with minimal duplication of functionality. <p> 5) Design a hardware implementation of the ANP according to the extended ISA with minimal microarchitectural and hardware changes to the existing PLM system. <p> 6) Increase the overall system performance for numeric intensive programs by an order of magnitude with the addition of the ANP co-processor. <p> 7) Develop a high performance math library to support frequently used operations based on the ANP/PLM architecture. <p> The processor is divided into five major functional units. The Bus Interface Unit (BIU) implements that co-processor interface protocol between ANP, PLM and the memory system. The Operand Coercion Unit (OCU) coerces mismatched data types and manages operands' vector length. The Execution Unit (EU), based on the Bipolar Integrated Technology (BIT) numeric chip set, is the numeric data path in the ANP. The scalar and vector Storage Unit (SU) consists of high speed multi-port register files which keep the Execution Unit at its maximum throughput. The writable control store, micro-sequencer and exception handling logic are located in the Micro Control Unit (MCU). <p> The ANP is currently being built using high speed TTL and ECL parts. This dissertation covers the design and simulation of the ANP and the evaluation of the ANP/PLM system using simulated execution of some modified Whetstone and Linpack benchmark programs.}
}

EndNote citation:

%0 Report
%A Yung, Robert
%T The Aquarius Numeric Processor
%I EECS Department, University of California, Berkeley
%D 1988
%@ UCB/CSD-88-418
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/1988/6038.html
%F Yung:CSD-88-418