Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Design and Implementation of A CMOS Chip for Prolog

Vason P. Srini, Jerric V. Tam, Tam M. Nguyen, Bruce K. Holmer, Yale N. Patt and Alvin M. Despain

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-88-412
March 1988

http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/CSD-88-412.pdf

We have designed and fabricated a high performance VLSI chip for executing Prolog programs using a 1.4 micron CMOS technology with two layers of metal. This chip implements a tagged architecture with hardware support for five stacks. The 32-bit data path of the chip contains a fast ALU, 64 registers in four groups, five counters, and six non-master/slave registers. The control is microprogrammed and uses a 512 X 160 bit ROM with four pages for fast microbranching. The chip operates at a cycle time of 100 ns (worst case) and has a size of 10 mm X 9 mm. A semicustom design methodology employing Mentor and NCR tools has been used in this design. The challenges involved in the design, verification, routing, and fabrication of the chip are described.


BibTeX citation:

@techreport{Srini:CSD-88-412,
    Author = {Srini, Vason P. and Tam, Jerric V. and Nguyen, Tam M. and Holmer, Bruce K. and Patt, Yale N. and Despain, Alvin M.},
    Title = {Design and Implementation of A CMOS Chip for Prolog},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1988},
    Month = {Mar},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/5862.html},
    Number = {UCB/CSD-88-412},
    Abstract = {We have designed and fabricated a high performance VLSI chip for executing Prolog programs using a 1.4 micron CMOS technology with two layers of metal. This chip implements a tagged architecture with hardware support for five stacks. The 32-bit data path of the chip contains a fast ALU, 64 registers in four groups, five counters, and six non-master/slave registers. The control is microprogrammed and uses a 512 X 160 bit ROM with four pages for fast microbranching. The chip operates at a cycle time of 100 ns (worst case) and has a size of 10 mm X 9 mm. A semicustom design methodology employing Mentor and NCR tools has been used in this design. The challenges involved in the design, verification, routing, and fabrication of the chip are described.}
}

EndNote citation:

%0 Report
%A Srini, Vason P.
%A Tam, Jerric V.
%A Nguyen, Tam M.
%A Holmer, Bruce K.
%A Patt, Yale N.
%A Despain, Alvin M.
%T Design and Implementation of A CMOS Chip for Prolog
%I EECS Department, University of California, Berkeley
%D 1988
%@ UCB/CSD-88-412
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/5862.html
%F Srini:CSD-88-412