Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Mocha Chip: A Graphical Programming System for IC Module Assembly

Robert Nelson Mayo

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-88-393
December 1987

http://www.eecs.berkeley.edu/Pubs/TechRpts/1988/CSD-88-393.pdf

Mocha Chip is a system for designing module generators. There are two unique aspects to this system: diagrams are used to represent the the structure of a module generator, and assembly primitives ensure that the generated layout obeys geometrical design rules and is properly connected.

Module generators are created using hierarchical diagrams rather than programs. The idea is to draw diagrams describing the topology of a class of modules, and to parameterize the diagrams to indicate how the individual modules differ. Parameterization is done using Lisp and special built-in cells that provide graphical representations of iteration and conditional selection. The diagrams may be considered to be a graphical programming language tailored to IC design.

Describing module generators with graphics rather than text adds flexibility to the module generator. Textual languages, such as programming languages, tend to obscure the geometrical relationships. Mocha Chip separates out the module structure and represents it graphically, resulting in module generators that are easier to design and modify. Openness and ease of modification are important since users need to tailor module generators to produce specialized modules.

Layout for a module is produced using two pairwise assembly operators that take pieces of layout and combine them to form a larger piece. The tile-packing operator aligns user-specified rectangles. The river-route-space operator uses two phases. The routing phase connects ports that do not line up exactly, and the cell spacing phase places the cells and routing as close together as rules allow.

The assembly process guarantees that no geometrical design rules will be violated and that the proper connections will be made. In other tile-based module generation systems, the user must manually check to make sure that all possible combinations of tiles will fit together properly. This is impractical for module generators that have a large number of tiles and options. The connection operator automatically ensures that the proper connections will be made and that no geometrical design rules will be violated.

Advisor: John K. Ousterhout


BibTeX citation:

@phdthesis{Mayo:CSD-88-393,
    Author = {Mayo, Robert Nelson},
    Title = {Mocha Chip: A Graphical Programming System for IC Module Assembly},
    School = {EECS Department, University of California, Berkeley},
    Year = {1987},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5855.html},
    Number = {UCB/CSD-88-393},
    Abstract = {Mocha Chip is a system for designing module generators. There are two unique aspects to this system: diagrams are used to represent the the structure of a module generator, and assembly primitives ensure that the generated layout obeys geometrical design rules and is properly connected. <p>Module generators are created using hierarchical diagrams rather than programs. The idea is to draw diagrams describing the topology of a class of modules, and to parameterize the diagrams to indicate how the individual modules differ. Parameterization is done using Lisp and special built-in cells that provide graphical representations of iteration and conditional selection. The diagrams may be considered to be a graphical programming language tailored to IC design. <p>Describing module generators with graphics rather than text adds flexibility to the module generator. Textual languages, such as programming languages, tend to obscure the geometrical relationships. Mocha Chip separates out the module structure and represents it graphically, resulting in module generators that are easier to design and modify. Openness and ease of modification are important since users need to tailor module generators to produce specialized modules. <p>Layout for a module is produced using two pairwise assembly operators that take pieces of layout and combine them to form a larger piece. The tile-packing operator aligns user-specified rectangles. The river-route-space operator uses two phases. The routing phase connects ports that do not line up exactly, and the cell spacing phase places the cells and routing as close together as rules allow. <p>The assembly process guarantees that no geometrical design rules will be violated and that the proper connections will be made. In other tile-based module generation systems, the user must manually check to make sure that all possible combinations of tiles will fit together properly. This is impractical for module generators that have a large number of tiles and options. The connection operator automatically ensures that the proper connections will be made and that no geometrical design rules will be violated.}
}

EndNote citation:

%0 Thesis
%A Mayo, Robert Nelson
%T Mocha Chip: A Graphical Programming System for IC Module Assembly
%I EECS Department, University of California, Berkeley
%D 1987
%@ UCB/CSD-88-393
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5855.html
%F Mayo:CSD-88-393