# Circuit Design Techniques for a Floating-Point Processor

### Timothy Hu

###
EECS Department

University of California, Berkeley

Technical Report No. UCB/CSD-87-372

September 1987

### http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-372.pdf

This report presents some novel circuit design techniques used in the datapath of the SPUR floating-point unit. Three most interesting circuit blocks are discussed which include a fast adder, a leading one detector and a shifter. Mixed logic with static and dynamic circuits are used. The chip is implemented in a 1.6 micron, N-well, double-metal CMOS process (HP CMOS40).

The timing and area of the above three modules are as follows:

66 bit adder

* Delay - Crystal 36 ns, SPICE 33 ns

* Size - 4757 x 553 lambda, which is 3806 x 442 um.

67 bit Leading one detector

* Delay - Crystal 20.5 ns, SPICE 18 ns

* Size - 4901 x 463 lambda, which is 3920 x 320 um.

67 bit shifter with Sticky Logic

* Delay - Shifting 15 ns, Sticky bit (latched into output latch) 25 ns

* Size - The whole module with decoder is 5359 x 1414 lambda, which is 4287 x 1131 um.

BibTeX citation:

@techreport{Hu:CSD-87-372, Author = {Hu, Timothy}, Title = {Circuit Design Techniques for a Floating-Point Processor}, Institution = {EECS Department, University of California, Berkeley}, Year = {1987}, Month = {Sep}, URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5810.html}, Number = {UCB/CSD-87-372}, Abstract = {This report presents some novel circuit design techniques used in the datapath of the SPUR floating-point unit. Three most interesting circuit blocks are discussed which include a fast adder, a leading one detector and a shifter. Mixed logic with static and dynamic circuits are used. The chip is implemented in a 1.6 micron, N-well, double-metal CMOS process (HP CMOS40). <p>The timing and area of the above three modules are as follows: <br />66 bit adder <br /> * Delay - Crystal 36 ns, SPICE 33 ns <br /> * Size - 4757 x 553 lambda, which is 3806 x 442 um. <br />67 bit Leading one detector <br /> * Delay - Crystal 20.5 ns, SPICE 18 ns <br /> * Size - 4901 x 463 lambda, which is 3920 x 320 um. <br />67 bit shifter with Sticky Logic <br /> * Delay - Shifting 15 ns, Sticky bit (latched into output latch) 25 ns <br /> * Size - The whole module with decoder is 5359 x 1414 lambda, which is 4287 x 1131 um.} }

EndNote citation:

%0 Report %A Hu, Timothy %T Circuit Design Techniques for a Floating-Point Processor %I EECS Department, University of California, Berkeley %D 1987 %@ UCB/CSD-87-372 %U http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5810.html %F Hu:CSD-87-372