Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Control Implementation for the SPUR Floating Point Coprocessor

Debby Jensen

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-87-369
August 1987

http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-369.pdf

SPUR is a RISC-based multiprocessor workstation being designed to facilitate parallel-processing research. Typically, RISC architectures achieve low performance levels for floating-point intensive applications, as the multiple-cycle floating-point instructions are not implemented in the hardware. In an attempt to raise these performance levels, the SPUR system provides floating-point support through an extended instruction set and a tightly-coupled floating-point coprocessor. This report documents the implementation of the control unit for this floating-point coprocessor; describing the coprocessor interface, control PLA definitions, the finite state machine, the dynamic cycle counter, the 4-stage load-store pipeline, and the random logic generated to drive the datapath modules. Implementation techniques and trade-offs are discussed; including design strategy, area and speed optimization, noise margin considerations, and delay balancing of the datapath control signals for clock skew minimization. Finally, simulation results obtained using SPICE, CRYSTAL, and MOSSIM are presented. The chip is implemented in 2-layer-metal 2um CMOS technology, and uses a four-phase non-overlapping clock with a target cycle time of approximately 100ns-140ns.


BibTeX citation:

@techreport{Jensen:CSD-87-369,
    Author = {Jensen, Debby},
    Title = {Control Implementation for the SPUR Floating Point Coprocessor},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1987},
    Month = {Aug},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5289.html},
    Number = {UCB/CSD-87-369},
    Abstract = {SPUR is a RISC-based multiprocessor workstation being designed to facilitate parallel-processing research. Typically, RISC architectures achieve low performance levels for floating-point intensive applications, as the multiple-cycle floating-point instructions are not implemented in the hardware. In an attempt to raise these performance levels, the SPUR system provides floating-point support through an extended instruction set and a tightly-coupled floating-point coprocessor. This report documents the implementation of the control unit for this floating-point coprocessor; describing the coprocessor interface, control PLA definitions, the finite state machine, the dynamic cycle counter, the 4-stage load-store pipeline, and the random logic generated to drive the datapath modules. Implementation techniques and trade-offs are discussed; including design strategy, area and speed optimization, noise margin considerations, and delay balancing of the datapath control signals for clock skew minimization. Finally, simulation results obtained using SPICE, CRYSTAL, and MOSSIM are presented. The chip is implemented in 2-layer-metal 2um CMOS technology, and uses a four-phase non-overlapping clock with a target cycle time of approximately 100ns-140ns.}
}

EndNote citation:

%0 Report
%A Jensen, Debby
%T Control Implementation for the SPUR Floating Point Coprocessor
%I EECS Department, University of California, Berkeley
%D 1987
%@ UCB/CSD-87-369
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5289.html
%F Jensen:CSD-87-369