Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Design of CPU Cache Memories

Alan Jay Smith

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-87-357
June 1987

http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-357.pdf

We present an overview of the current issues in the design of CPU cache memories. Our stress is on those issues of greatest concern to cache designers and builders, including line size, associativity, real vs. virtual addressing, main memory update algorithm, split (data/instructions) cache vs. unified cache, cache consistency mechanisms, cache size and number of cache levels. Brief mention is made of other aspects of cache and S-unit design. The Fairchild CLIPPER(tm) is used as an example of modern cache memory design.


BibTeX citation:

@techreport{Smith:CSD-87-357,
    Author = {Smith, Alan Jay},
    Title = {Design of CPU Cache Memories},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1987},
    Month = {Jun},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5288.html},
    Number = {UCB/CSD-87-357},
    Abstract = {We present an overview of the current issues in the design of CPU cache memories. Our stress is on those issues of greatest concern to cache designers and builders, including line size, associativity, real vs. virtual addressing, main memory update algorithm, split (data/instructions) cache vs. unified cache, cache consistency mechanisms, cache size and number of cache levels. Brief mention is made of other aspects of cache and S-unit design. The Fairchild CLIPPER(tm) is used as an example of modern cache memory design.}
}

EndNote citation:

%0 Report
%A Smith, Alan Jay
%T Design of CPU Cache Memories
%I EECS Department, University of California, Berkeley
%D 1987
%@ UCB/CSD-87-357
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/5288.html
%F Smith:CSD-87-357