Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Time-Optimal Design of a CMOS Adder

Belle W. Y. Wei, Clark D. Thompson and Yih-Farn Chen

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-86-252
August 1985

http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-252.pdf

In this paper, we present a systematic method of implementing a VLSI parallel adder. First, we define a family of adders, based on a modular design. Our design uses three types of component cells, which we implement in static CMOS. We then formulate the adder design as a dynamic programming problem, optimizing with respect to time. As a result, we have found the fastest 32-bit CMOS adder in our design family.


BibTeX citation:

@techreport{Wei:CSD-86-252,
    Author = {Wei, Belle W. Y. and Thompson, Clark D. and Chen, Yih-Farn},
    Title = {Time-Optimal Design of a CMOS Adder},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1985},
    Month = {Aug},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/6094.html},
    Number = {UCB/CSD-86-252},
    Abstract = {In this paper, we present a systematic method of implementing a VLSI parallel adder. First, we define a family of adders, based on a modular design. Our design uses three types of component cells, which we implement in static CMOS.  We then formulate the adder design as a dynamic programming problem, optimizing with respect to time. As a result, we have found the fastest 32-bit CMOS adder in our design family.}
}

EndNote citation:

%0 Report
%A Wei, Belle W. Y.
%A Thompson, Clark D.
%A Chen, Yih-Farn
%T Time-Optimal Design of a CMOS Adder
%I EECS Department, University of California, Berkeley
%D 1985
%@ UCB/CSD-86-252
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/6094.html
%F Wei:CSD-86-252