Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Power and Ground Requirements for a High-speed 32 Bit Computer Chip Set

John Keller

EECS Department
University of California, Berkeley
Technical Report No. UCB/CSD-86-253
August 1985

http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-253.pdf

The trend, as technology advances, is for VLSI implementations of computer systems to use increasingly wider busses and faster clock rates. This report illustrates how the trend affects integrated circuit design in the areas of power and ground design, and output pads. The first section of the report discusses the circuit design issues of inductance effects, CMOS noise margins, clean and dirty supply lines, pad loading and delay, process variation effects, and pad driver design approaches. The second section is an in depth description of the technique used and results obtained for inductance characterization of pin grid arrays. Following that is a section discussing design issues for input and output pad cells, along with a description of the pad cells developed for the Berkeley SPUR project.


BibTeX citation:

@techreport{Keller:CSD-86-253,
    Author = {Keller, John},
    Title = {Power and Ground Requirements for a High-speed 32 Bit Computer Chip Set},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1985},
    Month = {Aug},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/6073.html},
    Number = {UCB/CSD-86-253},
    Abstract = {The trend, as technology advances, is for VLSI implementations of computer systems to use increasingly wider busses and faster clock rates. This report illustrates how the trend affects integrated circuit design in the areas of power and ground design, and output pads. The first section of the report discusses the circuit design issues of inductance effects, CMOS noise margins, clean and dirty supply lines, pad loading and delay, process variation effects, and pad driver design approaches. The second section is an in depth description of the technique used and results obtained for inductance characterization of pin grid arrays. Following that is a section discussing design issues for input and output pad cells, along with a description of the pad cells developed for the Berkeley SPUR project.}
}

EndNote citation:

%0 Report
%A Keller, John
%T Power and Ground Requirements for a High-speed 32 Bit Computer Chip Set
%I EECS Department, University of California, Berkeley
%D 1985
%@ UCB/CSD-86-253
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/6073.html
%F Keller:CSD-86-253